In [1] the authors use a lemma to prove their Theorem 1 (pp. 352-353). While the lemma is true, there is a defect in its proof, for one cannot assume that each of the symbols appearing as a type IV reference is in t(E...
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In [1] the authors use a lemma to prove their Theorem 1 (pp. 352-353). While the lemma is true, there is a defect in its proof, for one cannot assume that each of the symbols appearing as a type IV reference is in t(Ek , s). Using their example (p. 350) as a reference string with k = 12, t(E12 , 3) is 534 and lacks the two symbols (1 and 2) which appear as type IV references.
The traditional page-grained buffer manager in database systems has a low hit ratio when only a few tuples within a page are frequently accessed. To handle this issue, this paper proposes a new buffering scheme called...
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The traditional page-grained buffer manager in database systems has a low hit ratio when only a few tuples within a page are frequently accessed. To handle this issue, this paper proposes a new buffering scheme called the AMG-Buffer (Adaptive Multi-Grained Buffer). AMG-Buffer proposes to use two page buffers and a tuple buffer to organize the whole buffer. In this way, the AMG-Buffer can hold more hot tuples than a single page-grained buffer. Further, we notice that the tuple buffer may cause additional read I/Os when writing dirty tuples into disks. Thus, we introduce a new metric named clustering rate to quantify the hot-tuple rate in a page. The use of the tuple buffer is determined by the clustering rate, allowing the AMG-Buffer to adapt to different workloads. We conduct experiments on various workloads to compare the AMG-Buffer with several existing schemes, including LRU, LIRS, CFLRU, CFDC, and MG-Buffer. The results show that AMG-Buffer can significantly improve the hit ratio and reduce I/Os compared to its competitors. Moreover, the AMG-Buffer achieves the best performance on a dynamic workload as well as on a large data set, suggesting its adaptivity and scalability to changing workloads.
The embedded processor performance is significantly influenced by cache whose performance depend on its architecture parameters. Meanwhile, In order to overcome the non-timing accurate flaw of software simulation meth...
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The embedded processor performance is significantly influenced by cache whose performance depend on its architecture parameters. Meanwhile, In order to overcome the non-timing accurate flaw of software simulation method, In this paper, a hardware emulation method--RTL level models is used for CPU and cache controller, while circuit model for cache memory cell--is adopted to do research on cache performance. A more accurate design space, miss rate and cycle trend influenced by cache parameters, is presented. Compared with Round Robin, it shows that miss rate and cycle number of instruction cache is reduced by 22.08% and 20.36%, respectively, because PseudoLRU is adopted.
The embedded processor performance is significantly influenced by cache whose performance depend on its architecture parameters. Meanwhile, In order to overcome the non-timing accurate flaw of software simulation meth...
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The embedded processor performance is significantly influenced by cache whose performance depend on its architecture parameters. Meanwhile, In order to overcome the non-timing accurate flaw of software simulation method, In this paper, a hardware emulation method --RTL level models is used for CPU and cache controller, while circuit model for cache memory cell--is adopted to do research on cache performance . A more accurate design space, miss rate and cycle trend influenced by cache parameters, is presented. Compared with Round Robin, it shows that miss rate and cycle number of instruction cache is reduced by 22.08% and 20.36%, respectively, because Pseudo- LRU is adopted.
Content Centric Networking (CCN) is a new and promising architecture that can provide better security and much improved content delivery service than the current Internet. Each router in CCN has a content store that c...
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ISBN:
(纸本)9781457720529
Content Centric Networking (CCN) is a new and promising architecture that can provide better security and much improved content delivery service than the current Internet. Each router in CCN has a content store that caches objects according to a replacement algorithm and a pending interest table that stores pending requests waiting for matching objects. We propose a novel and flexible resource management system where the content store can store objects as well as pending requests. To each pending request, we add control fields that can be used to control caching resources according to a given objective function. We examine several applications that can benefit from using the proposed resource management system. The experimental results quantify key performance improvements.
This paper presents a new buffer cache management scheme called DABC-NV for mixed MLC and SLC flash memories as the secondary storage and both byte-accessible NVRAM and conventional volatile RAM as their buffer caches...
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ISBN:
(纸本)9781424449316
This paper presents a new buffer cache management scheme called DABC-NV for mixed MLC and SLC flash memories as the secondary storage and both byte-accessible NVRAM and conventional volatile RAM as their buffer caches. DABC-NV has four salient features. First, it allocates buffer cache space to MLC and SLC flash memories based on their I/O costs and then dynamically adjusts the allocated size according to the evolution of workloads. Second, it separately exploits read and write histories of block references, and thus it estimates future references of each operation more precisely. Third, it guarantees the complete consistency of write I/Os since all dirty data are cached in nonvolatile buffer caches. Fourth, metadata lists are maintained separately from cached blocks. This allows more efficient management of volatile and nonvolatile buffer caches based on read and write histories, respectively. Trace-driven simulations show that DABC-NV improves the I/O performance of embedded systems significantly. Specifically, it reduces I/O time by 24% on average compared to the CLOCK-NV algorithm.
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