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algorithms IMPLEMENTING DISTRIBUTED shared memory

COMPUTER 1990年第5期23卷 54-64页

作者： STUMM, M ZHOU, SN UNIV TORONTO DEPT COMP SCITORONTO M5S 1A4ONTARIOCANADA

Four basic algorithms for implementing distributed shared memory are compared. Conceptually, these algorithms extend local virtual address spaces to span multiple hosts connected by a local area network, and some of them can easily be integrated with the hosts' virtual memory systems. The merits of distributed shared memory and the assumptions made with respect to the environment in which the shared memory algorithms are executed are described. The algorithms are then described, and a comparative analysis of their performance in relation to application-level access behavior is presented. It is shown that the correct choice of algorithm is determined largely by the memory access behavior of the applications. Two particularly interesting extensions of the basic algorithms are described, and some limitations of distributed shared memory are noted

关键词： application-level access behavior distributed shared memory environment local area network local area networks local virtual address spaces memory access behavior multiple hosts multiprogramming network operating systems performance shared memory algorithms virtual memory systems

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Cache-Sensitive MapReduce DGEMM algorithms for shared memory Architectures

Cache-Sensitive MapReduce DGEMM Algorithms for Shared Memory...

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Symposium of the South African Institute for Computer Scientists and Information Technologists (SAICSIT)

作者： Nimako, Gideon Otoo, E. J. Ohene-Kwofie, Daniel Univ Witwatersrand Sch Comp Sci Johannesburg South Africa

ISBN: (纸本)9781450313087

Parallelism in linear algebra libraries is a common approach to accelerate numerical and scientific applications. Matrix-matrix multiplication is one of the most widely used computations in scientific and numerical algorithms. Although a number of matrix multiplication algorithms exist for distributed memory environments (e.g., Cannon, Fox, PUMMA, SUMMA), matrix-matrix multiplication algorithms for shared memory and SMP architectures have not been extensively studied. In this paper, we present a fast matrix-matrix multiplication algorithm for multi-core and SMP architectures using the MapReduce framework. memory-resident linear algebra algorithms suffer performance losses on modern multi-core architectures because of the increasing performance gap between the CPU and main memory. To allow such compute-intensive algorithms to exploit the full potential of the program's inherent instruction level parallelism, the adverse effect of the processor-memory performance gap should be minimized. We present a cache-sensitive MapReduce matrix multiplication algorithm that fully exploits memory bandwidth and minimize cache misses and conflicts. Our experimental results show that the two algorithms outperform existing matrix multiplication algorithms for shared-memory architectures such as those given in the Phoenix, PLASMA and LAPACK libraries.

关键词： Cache-Sensitive shared memory algorithms MapReduce Matrix Multiplication

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Vascular System Modeling in Parallel Environment - Distributed and shared memory Approaches

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IEEE TRANSACTIONS ON INFORMATION TECHNOLOGY IN BIOMEDICINE 2011年第4期15卷 668-672页

作者： Jurczuk, Krzysztof Kretowski, Marek Bezy-Wendling, Johanne Bialystok Tech Univ Fac Comp Sci PL-15351 Bialystok Poland INSERM U642 F-35000 Rennes France Univ Rennes 1 LTSI F-35000 Rennes France

This paper presents two approaches in parallel modeling of vascular system development in internal organs. In the first approach, new parts of tissue are distributed among processors and each processor is responsible for perfusing its assigned parts of tissue to all vascular trees. Communication between processors is accomplished by passing messages, and therefore, this algorithm is perfectly suited for distributed memory architectures. The second approach is designed for shared memory machines. It parallelizes the perfusion process during which individual processing units perform calculations concerning different vascular trees. The experimental results, performed on a computing cluster and multicore machines, show that both algorithms provide a significant speedup.

关键词： Computational modeling distributed memory algorithms parallel computing shared memory algorithms vascular system

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A shared-memory Algorithm for Updating Tree-Based Properties of Large Dynamic Networks

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IEEE TRANSACTIONS ON BIG DATA 2022年第2期8卷 302-317页

作者： Srinivasan, Sriram Pollard, Samuel D. Norris, Boyana Das, Sajal K. Bhowmick, Sanjukta Univ Nebraska Omaha Dept Comp Sci Omaha NE 68182 USA Univ Oregon Dept Comp & Informat Sci Eugene OR 97403 USA Missouri Univ Sci & Technol Dept Comp Sci Rolla MO 65409 USA

This paper presents a network-based template for analyzing large-scale dynamic data. Specifically, we propose a novel shared-memory parallel algorithm for updating tree-based structures or properties, such as connected components (CC) and minimum spanning trees (MST), on dynamic networks. The underlying idea is to update the information in a rooted tree data structure that stores the edges of the network that are most relevant to the analysis. Extensive experiments on real-world and synthetic networks demonstrate that, with the exception of the inherently sequential component for creating the rooted tree, our proposed updatiing algorithm is scalable and, in most cases, also requires significantly less memory, energy, and time than recomputing-from-scratch algorithm. To the best of our knowledge, this is the first parallel algorithm for updating MST on weighted dynamic networks. The rooted-tree based framework that we propose in this paper can be extended for updating other weighted and unweighted tree-based properties such as single source shortest path and betweenness and closeness centrality.

关键词： Heuristic algorithms Data structures Parallel algorithms Image edge detection Big Data Partitioning algorithms Maintenance engineering Dynamic networks minimum spanning tree connected components shared memory algorithms

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Synchron-ITS: An Interactive Tutoring System to Teach Process Synchronization and shared memory Concepts in an Operating Systems Course

Synchron-ITS: An Interactive Tutoring System to Teach Proces...

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17th International Conference on Collaboration Technologies and Systems (CTS)

作者： Putchala, Manoj Kumar Bryant, Adam R. Wright State Univ Dept Comp Sci & Engn Dayton OH 45435 USA

ISBN: (纸本)9781509022991

Operating Systems (OS) is a course in undergraduate computer science curricula to teach students concepts relating to the environment on which their applications run. In practice, OS software is very complicated, and the internal processes and mechanisms are often difficult for students to grasp, particularly those that still struggle with programming. Many OS courses are taught by describing high-level abstractions of structures and algorithms from a textbook, and then providing homework or project assignments that, in the interest of being tractable for the student, may be disconnected from the way an operating system actually performs its tasks. These methods only present a theoretical display of essential concepts which lack concrete examples to anchor the concepts. What many students need is a way to connect the low-level details of an operating system's implementation with the high-level abstractions provided in the class, all while being accessible to people who are still improving newly acquired programming skills. To bridge the gap between OS theory and implementation, we propose an interactive tutoring system to present the concepts involved with process synchronization and shared memory management. In this paper, first, we discuss the research performed to frame the requirements for the tool development. Second, we describe the design architecture, concepts involved and features of the tool. Third, we outline the test plan, user experiments and future improvements planned for this system.

关键词： Operating systems interactive tutoring systems process synchronization shared memory algorithms

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Migration in Hardware Transactional memory on Asymmetric Multiprocessor

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IEEE ACCESS 2021年 9卷 69346-69364页

作者： Sustran, Zivojin Protic, Jelica Univ Belgrade Sch Elect Engn Belgrade 11120 Serbia

In this paper, a system is presented which implements transactions migration to an asymmetric multiprocessor in order to decrease the probability of conflicts and improve execution performance. Applications parallelization makes programming and testing much more difficult, so the goal is to avoid putting additional burden on a programmer. Therefore, the proposed solution should be fully implemented in hardware. In the asymmetric multiprocessor that is analyzed, all cores have the same instruction set, but they are asymmetric in terms of microarchitectural properties, so that N - 1 "small'' cores are identical, while the N-th "big'' core is different, as it provides better performance and higher capacities of its units. The idea is to perform transaction migration from the "small'' core to the "big'' one, based on the history of transaction execution. The experiments were performed using a significantly upgraded Gem5 simulator and eight parallel applications from the STAMP benchmark suite. The experimental results show the speedup and the rate of successfully executed transactions for five different multiprocessor configurations, including symmetric and asymmetric multiprocessors with or without transaction migration. The improvement our algorithm achieves for suitable applications is up to 14% (10% on average) in turnaround time compared to the solutions which do not make use of asymmetry for scheduling transactions.

关键词： shared memory algorithms multicore architectures hardware transactional memory asymmetric multiprocessor thread migration

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Sharing memory between Byzantine Processes Using Policy-Enforced Tuple Spaces

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IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 2009年第3期20卷 419-432页

作者： Bessani, Alysson Neves Correia, Miguel Fraga, Joni da Silva Lung, Lau Cheuk Univ Lisbon Fac Ciencias Dept Informat P-1749016 Lisbon Portugal Univ Fed Santa Catarina DAS Dept Automacao & Sistemas BR-88040900 Florianopolis SC Brazil Univ Fed Santa Catarina INE Dept Informat & Estat BR-88040900 Florianopolis SC Brazil

Despite the large amount of Byzantine fault-tolerant algorithms for message-passing systems designed through the years, only recent algorithms for the coordination of processes subject to Byzantine failures using shared memory have appeared. This paper presents a new computing model in which shared memory objects are protected by fine-grained access policies, and a new shared memory object, the Policy-Enforced Augmented Tuple Space (PEATS). We show the benefits of this model by providing simple and efficient consensus algorithms. These algorithms are much simpler and require less shared memory operations, using also less memory bits than previous algorithms based on access control lists (ACLs) and sticky bits. We also prove that PEATS objects are universal, i.e., that they can be used to implement any other shared memory object, and present lock-free and wait-free universal constructions.

关键词： Byzantine fault-tolerance shared memory algorithms tuple spaces consensus universal constructions

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A Conflict-Resilient Lock-Free Linearizable Calendar Queue

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ACM TRANSACTIONS ON PARALLEL COMPUTING 2024年第1期11卷 1-32页

作者： Marotta, Romolo Ianni, Mauro Pellegrini, Alessandro Quaglia, Francesco Univ Roma Tor Vergata I-00100 Rome Italy Lockless Srl I-00100 Rome Italy

In the last two decades, great attention has been devoted to the design of non-blocking and linearizable data structures, which enable exploiting the scaled-up degree of parallelism in off-the-shelf shared-memory multi-core machines. In this context, priority queues are highly challenging. Indeed, concurrent attempts to extract the highest-priority item are prone to create detrimental thread conflicts that lead to abort/retry of the operations. In this article, we present the first priority queue that jointly provides: (i) lock-freedom and linearizability;(ii) conflict resiliency against concurrent extractions;(iii) adaptiveness to different contention profiles;and (iv) amortized constant-time access for both insertions and extractions. Beyond presenting our solution, we also provide proof of its correctness based on an assertional approach. Also, we present an experimental study on a 64-CPU machine, showing that our proposal provides performance improvements over state-of-the-art non-blocking priority queues.

关键词： Data structures design and analysis shared memory algorithms concurrent algorithms non-blocking priority queue pending event set

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Real-Time Decompression and Rasterization of Massive Point Clouds

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PROCEEDINGS OF THE ACM ON COMPUTER GRAPHICS AND INTERACTIVE TECHNIQUES 2024年第3期7卷 1-15页

作者： Goel, Rahul Schuetz, Markus Narayanan, P. J. Kerbl, Bernhard IIIT Hyderabad Hyderabad India TU Wien Vienna Austria

Large-scale capturing of real-world scenes as 3D point clouds (e.g., using LIDAR scanning) generates billions of points that are challenging to visualize. High storage requirements prevent the quick and easy inspection of captured datasets on user-grade hardware. The fastest real-time rendering methods are limited by the available GPU memory and render only around 1 billion points interactively. We show that we can achieve state-of-the-art in both while simultaneously supporting datasets that surpass the capabilities of other methods. We present an on-the-fly point cloud decompression scheme that tightly integrates with software rasterization to reduce on-chip memory requirements by more than 4×. Our method compresses geometry losslessly and provides high visual quality at real-time framerates. We use a GPU-friendly, clipped Huffman encoding for compression. Point clouds are divided into equal-sized batches, which are Huffman-encoded independently. Batches are further subdivided to form easy-to-consume streams of data for massively parallel execution. The compressed point clouds are stored in an access-aware manner to achieve coherent GPU memory access and a high L1 cache hit rate at render time. Our approach can decompress and rasterize up to 120 million Huffman-encoded points per millisecond on-the-fly. We evaluate the quality and performance of our approach on various large datasets against the fastest competing methods. Our approach renders massive 3D point clouds at competitive frame rates and visual quality while consuming significantly less memory, thus unlocking unprecedented performance for the visualization of challenging datasets on commodity GPUs.

关键词： CCS Concepts Computing methodologies -> Rasterization shared memory algorithms

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Mini-batching with Fused Training and Testing for Data Streams Processing on the Edge 21

Mini-batching with Fused Training and Testing for Data Strea...

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21st ACM International Conference on Computing Frontiers (CF)

作者： Luna, Reginaldo Cassales, Guilherme Pfahringer, Bernhard Bifet, Albert Gomes, Heitor Murilo Senger, Hermes Univ Fed Sao Carlos Sao Carlos Brazil Univ Waikato Hamilton New Zealand Victoria Univ Wellington Wellington New Zealand

ISBN: (纸本)9798400705977

Edge Computing (EC) has emerged as a solution to reduce energy demand and greenhouse gas emissions from digital technologies. EC supports low latency, mobility, and location awareness for delay-sensitive applications by bridging the gap between cloud computing services and end-users. Machine learning (ML) methods have been applied in EC for data classification and information processing. Ensemble learners have often proven to yield high predictive performance on data stream classification problems. Mini-batching is a technique proposed for improving cache reuse in multi-core architectures of bagging ensembles for the classification of online data streams, which benefits application speedup and reduces energy consumption. However, the original mini-batching presents limited benefits in terms of cache reuse and it hinders the accuracy of the ensembles (i.e., their capacity to detect behavior changes in data streams). In this paper, we improve mini-batching by fusing continuous training and test loops for the classification of data streams. We evaluated the new strategy by comparing its performance and energy efficiency with the original mini-batching for data stream classification using six ensemble algorithms and four benchmark datasets. We also compare mini-batching strategies with two hardware-based strategies supported by commodity multi-core processors commonly used in EC. Results show that mini-batching strategies can significantly reduce energy consumption in 95% of the experiments. Mini-batching improved energy efficiency by 96% on average and 169% in the best case. Likewise, our new mini-batching strategy improved energy efficiency by 136% on average and 456% in the best case. These strategies also support better control of the balance between performance, energy efficiency, and accuracy.

关键词： Computing methodologies Parallel computing methodologies Parallel algorithms shared memory algorithms

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