This paper suggests an automated validation approach in testing advanced digital signal processing algorithms. These algorithms, which are intended for the implementation of the base band processor of software defined...
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This paper suggests an automated validation approach in testing advanced digital signal processing algorithms. These algorithms, which are intended for the implementation of the base band processor of software defined radios, are developed in software (digital signal processors DSP) and hardware (FPGA) environments in order to meet real-time and offline requirements. The automation of the testing of such algorithms enhances their robustness and accuracy, reduces human-computer interaction, decreases the latency between tests by reusing unmodified program code
Since human physiological signals (e.g., respiration and heart rate) generate very small Doppler shifts, they are highly susceptible to being masked by strong clutter backgrounds. The main research focus of this proje...
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ISBN:
(数字)9798331504960
ISBN:
(纸本)9798331504977
Since human physiological signals (e.g., respiration and heart rate) generate very small Doppler shifts, they are highly susceptible to being masked by strong clutter backgrounds. The main research focus of this project is to accurately extract weak targets (i.e., vital signs) from complex environments. The signals received by BioRadar contain vital signs signals and clutter signals. Based on the analysis of the collected data, it is known that vital signals have low signal-to-noise ratio and are characterized by quasi-periodicity and multiple harmonics; whereas clutter can be manifested as Gaussian colored noise. For this reason, this study translates the bio-radar signalprocessing into the problems of harmonic modeling, clutter suppression, and signal-to-noise ratio enhancement in the presence of Gaussian colored noise. The research objective is to extract the weak vital sign signals of human body from the complex background by machine learning techniques. In order to effectively extract physiological signals such as respiration and heart rate, this paper employ an ultra-wideband bio-radar system and advanced signal processing algorithms, and the experimental results show that the respiratory signal of participant 1 at 0 s is 2.1 mV, the heartbeat signal is 1.0 mV, and the suppressed clutter signal is 0.1 mV, which effectively suppresses the clutter interference with high accuracy and reliability.
This paper presents a design environment for efficiently generating application-specific intellectual property (IP) cores for system level signal processing algorithms. We present our view of a framework that combines...
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This paper presents a design environment for efficiently generating application-specific intellectual property (IP) cores for system level signal processing algorithms. We present our view of a framework that combines common electronic design automation (EDA) tools to alleviate the designer from manually constructing the hardware models and analyzing their performance. We use our framework to efficiently implement design optimizations that improve the performance of the overall hardware architectures. Our framework is well suited for designers with a range of signalprocessing and hardware expertise. Our framework generates the dedicated IP cores and estimates the performance such as area, critical path delay, and latency within seconds. Parts of our framework also compare different hardware designs for various digital signalprocessing (DSP) algorithms and allows the designer to make architectural decisions earlier in the hardware design process. We use a GUI-based framework invoked from MATLAB to automatically build and analyze the hardware designs. Our framework generates efficient hardware designs described in SystemC and Verilog code, along with the performance metrics for each architecture. We illustrate the use of our framework by exploring and analyzing architectural variations of two case studies: finite impulse response (FIR) filters and adaptive channel equalizers
In applications, such as high quality audio, that need more than 16 bits of precision, the processing of signals on a 16-bit DSP requires double precision computation and is hence time consuming. Since in residue numb...
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In applications, such as high quality audio, that need more than 16 bits of precision, the processing of signals on a 16-bit DSP requires double precision computation and is hence time consuming. Since in residue number system (RNS), the high precision data is decomposed to a lower precision for its processing, in this paper, we propose RNS for increasing the performance of such applications implemented on a single processor. We apply multirate architectures and also suggest some architectural extensions to the processor to further enhance the performance. The results show that performance improvement of more than 57% can be achieved with these implementations. We also show that the power dissipation can be significantly reduced with such implementations.
The paper is concerned with developing novel multiuser detection algorithms. The main stress is on blind decorrelation of weakly stationary processes which can successfully combat multiuser interference (MUI) and inte...
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The paper is concerned with developing novel multiuser detection algorithms. The main stress is on blind decorrelation of weakly stationary processes which can successfully combat multiuser interference (MUI) and intersymbol interference (ISI). The detector architecture includes an adaptive channel identifier (capable of blind decorrelation), followed by a stochastic Hopfield net which performs the task of multiuser detection. The key contribution to mobile communication lies in two factors: (i) blind decorrelation which can identify the channel even in the case of fading; (ii) the use of the stochastic Hopfield net which can guarantee good performance due to its ability to reach the global minimum of the associated quadratic form. The proposed detector structure is proven to be superior to the RAKE or Viterbi receivers. The results are demonstrated by simulations as well.
This paper describes a C++ class, fixpt /spl minus/ a new data type used for development of fixed point algorithms. Fixpt is designed to reduce the development time incurred during the conversion of floating point alg...
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This paper describes a C++ class, fixpt /spl minus/ a new data type used for development of fixed point algorithms. Fixpt is designed to reduce the development time incurred during the conversion of floating point algorithms into equivalent fixed point implementations on fixed point processors or custom designed ASIC hardware. Fixpt allows each variable in a C++ program to be declared with a user defined whole and fractional size. For example, the C++ statement "fixpt var1 (6,10);" creates a fixpt variable with 6 bits for the whole part and 10 bits for the fractional part. During program execution, the fixpt class handles detection and management of overflow and underflow conditions, thus allowing the programmer to quickly identify which variables are incorrectly sized. The fixpt class also provides extensive debugging aids and user definable overflow function. Basic functionality of the class, along with comparisons between floating point and fixpt algorithms, such as audio decompression, are presented.< >
The CORDIC (coordinate rotation digital computer) algorithm is an iterative arithmetic procedure for generalized vector rotations. For applications where the angle of rotation is known in advance, it is possible to re...
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The CORDIC (coordinate rotation digital computer) algorithm is an iterative arithmetic procedure for generalized vector rotations. For applications where the angle of rotation is known in advance, it is possible to reduce the number of iterations through a technique (called angle recoding) in which the desired angle of rotation is encoded as a linear combination of very few elementary rotation angles. Unfortunately, an optimal encoding requires exhaustive search of exponentially growing number of possible combinations of these elementary angles. A Greedy algorithm which takes only O(n/sup 2/) operations was developed. It is proved that this algorithm is able to reduce the total number of elementary rotation angles by at least 50%. In the linear rotation case, it is shown that this proposed angle recoding scheme is equivalent to that of the modified Booth's recoding method. Potential applications of the angle recoding scheme to a number of rotation based digital signal processing algorithms are discussed.< >
Predicting the complexity of a signalprocessing task is a very difficult subject, mainly because the notion of complexity itself is not well defined. We propose to link the complexity to the predicted execution of an...
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Predicting the complexity of a signalprocessing task is a very difficult subject, mainly because the notion of complexity itself is not well defined. We propose to link the complexity to the predicted execution of an algorithm on a given platform or processor. To do so branches, arithmetic and memory operations are classified into different types of category. Then the number of time operations of each category executed is computed for the studied algorithm. Finally weights depending on the underlying architecture are used to sum up the contribution of each category to get the final complexity. Typical weights for two Pentium processors are presented and the validity of the prediction is verified for the case of a simple algorithm.
Product requirements often dictate the use of off-the-shelf processors for very fast signalprocessing applications. Additionally, restrictions on cost, power, or size/weight may preclude the use of specialized vector...
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Product requirements often dictate the use of off-the-shelf processors for very fast signalprocessing applications. Additionally, restrictions on cost, power, or size/weight may preclude the use of specialized vector processors for implementation of the algorithms. We discuss a new method for performing signed parallel processing in scalar, off-the-shelf processors for integerized signal processing algorithms. Uniform data precision may be used, but is not required for the method. It is shown that the reduction in execution cycles resulting from this implementation is approximately linear in the size of the registers, divided by the precision required.
A multiprocessor scheduler has been developed for scheduling signalprocessing and other algorithms on programmable digital signal processors that can be connected in a common-bus or hypercube topology. The scheduler ...
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A multiprocessor scheduler has been developed for scheduling signalprocessing and other algorithms on programmable digital signal processors that can be connected in a common-bus or hypercube topology. The scheduler requires an acyclic precedence graph of the algorithm and the cost of all interprocessor communications. The software tool permits the user to select from among three different scheduling algorithms. The first is a heuristic method, the second uses dynamic programming, and the third uses integer linear programming. Schedules for six practical signal processing algorithms are obtained, and throughput rates are compared to those obtained with uniprocessor implementation.< >
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