A high Level signalprocessing system is presented consisting of the abstract signalprocessing language SIPROL, a translator system and a general purpose signal processor GPSP. SIPROL is derived from PASCAL including...
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A high Level signalprocessing system is presented consisting of the abstract signalprocessing language SIPROL, a translator system and a general purpose signal processor GPSP. SIPROL is derived from PASCAL including useful extensions on abstract data types. A SIPROL program is compiled into an intermediate language program and then transformed onto various target machine levels by table-driven codegeneration. The hardware modules of the GPSP are derived from the virtual machine associated to the intermediate language. The kernel feature of the system facilitates a flexible transition and migration from software to hardware with respect to the signalprocessing speed requirements.
Based on simple comparison between a conventional navigation receiver and a GNSS software receiver, a generic GNSS receiver architecture is given, which focuses on the GPS IF signalprocessing algorithm in the channel...
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Based on simple comparison between a conventional navigation receiver and a GNSS software receiver, a generic GNSS receiver architecture is given, which focuses on the GPS IF signalprocessing algorithm in the channel. According to the channel states the algorithm falls into four parts: signal acquisition, confirmation, fine frequency estimation and tracking. A frequency domain acquisition based on FFT operation is proposed, but the acquisition results need to be confirmed because of the false alarm probability. signal confirmation is formed on the basis of the conventional threshold detection method using the changes in the Doppler shifts and code phases during several consecutive sampling periods. The fine frequency estimation adopts signalspsila phase relation obtained from FFT. signal tracking is a combination of a Costas Phase Look Loop (PLL) and a non-coherent Early-Late gate delay lock loop (DLL). At the end of the paper, the results of the experiments with real GPS IF signal confirm valid operation of the proposed GPS signalprocessing.
For implantable neural interface applications, it is important to compress data and analyze spike patterns across multiple channels in real time. Such a computational task for online neural data processing requires an...
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For implantable neural interface applications, it is important to compress data and analyze spike patterns across multiple channels in real time. Such a computational task for online neural data processing requires an innovative circuit-architecture level design approach for low-power, robust and area-efficient hardware implementation. Conventional microprocessor or Digital signalprocessing (DSP) chips would dissipate too much power and are too large in size for an implantable system. In this paper, we propose a novel hardware design approach, referred to as ldquoPreferential Designrdquo that exploits the nature of the neural signalprocessing algorithm to achieve a low-voltage, robust and area-efficient implementation using nanoscale process technology. The basic idea is to isolate the critical components with respect to system performance and design them more conservatively compared to the noncritical ones. This allows aggressive voltage scaling for low power operation while ensuring robustness and area efficiency. We have applied the proposed approach to a neural signalprocessing algorithm using the Discrete Wavelet Transform (DWT) and observed significant improvement in power and robustness over conventional design.
Based on the characteristics and parallel design research of multi-core and many-core hardware platforms, this paper proposes an adaptive parallel optimization design method for signalprocessing on multi-core and man...
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ISBN:
(数字)9798350369151
ISBN:
(纸本)9798350369168
Based on the characteristics and parallel design research of multi-core and many-core hardware platforms, this paper proposes an adaptive parallel optimization design method for signalprocessing on multi-core and many-core platforms. By employing a hardware platform architecture-aware approach and a multi-core segmented pipeline design, adaptive parallel optimization is achieved. The method was tested and verified using a two-stage FFT algorithm on the Phytium 2000+ platform. The test results indicate that through multiple iterations of optimization, adaptive high-performance parallel processing on multi-core and many-core platforms can be realized.
This paper presents a VLSI architecture for implementing the Partial-Rank Algorithm used in adaptive beamforming. The architecture depends on VLSI computational hardware for vector operations which are the main comput...
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This paper presents a VLSI architecture for implementing the Partial-Rank Algorithm used in adaptive beamforming. The architecture depends on VLSI computational hardware for vector operations which are the main computations needed for the algorithm. The systolic-like architecture presented is as flexible as the algorithm itself in the sense that higher order algorithms can be implemented by adding identical hardware. The implementation is shown to be extendable from an LMS algorithm to a full matrix algorithm.
In this paper, a tactile sensing system for an anthropomorphic robot hand is presented. The tactile sensing system is designed as a construction kit making it very versatile. The sensor data preprocessing is embedded ...
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In this paper, a tactile sensing system for an anthropomorphic robot hand is presented. The tactile sensing system is designed as a construction kit making it very versatile. The sensor data preprocessing is embedded into the hand's hardware structure and is fully integrated. The sensor system is able to gather tactile pressure profiles and to measure vibrations in the sensor's cover. Additionally to the introduction of the hardware, the signalprocessing and the classification of the acquired sensor data will be explained in detail. These algorithms make the tactile sensing system capable to detect contact points, to classify contact patterns and to detect slip conditions during object manipulation and grasping.
Aiming at the detection and imaging of targets in clutter, the parameters design and the optimization criterion based on the stepped frequency waveform were given. Meanwhile the signalprocessing algorithm was propose...
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Aiming at the detection and imaging of targets in clutter, the parameters design and the optimization criterion based on the stepped frequency waveform were given. Meanwhile the signalprocessing algorithm was proposed, which includes the method of measuring the radial velocity based on the frame PD processing, and the follow-up processing of echo reconstruction and synthesizing high range resolution (HRR) profiles. At last, combined with the parameters of a real radar system, simulation results validate the effectivity of the algorithm and the ability of extracting target information and synthesizing the one-dimension HRRP under the clutter background.
In order to give full play to the advantages of software defined chip hardware architecture, this paper designs a configuration mechanism of software defined chip applied in the field of signalprocessing. Firstly, th...
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ISBN:
(纸本)9781665487900
In order to give full play to the advantages of software defined chip hardware architecture, this paper designs a configuration mechanism of software defined chip applied in the field of signalprocessing. Firstly, this paper designs the configuration line execution iteration of PE (processing Element); Secondly, the iteration times of PE top layer are designed; Thirdly design the number of PEA (processing element array) top-level iterations; Finally, the implementation of matrix multiplication algorithm is used to analyze the hardware design results. Through simulation, the results show that, compared with TI c66x DSP, the clock cycle required to execute the same algorithm is reduced from 15325 to 200; The power consumption is reduced from 1092 mW to 420 mW, and the processing speed and power consumption are better than those of TI c66x DSP.
Two new methods developed to improve the classical preset time count rate meters by using the adaptive signalprocessing tools, are presented. An optimized detection algorithm that senses the change of the mean count ...
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Two new methods developed to improve the classical preset time count rate meters by using the adaptive signalprocessing tools, are presented. An optimized detection algorithm that senses the change of the mean count rate was implemented in both methods. Three low-pass filters of various structures with adaptive parameters to implement the control of the mean count rate error were considered. An adaptation algorithm for preset time interval calculations was devised and implemented in both methods differing only in the place of its execution (before or after the low-pass filters). The simulated and realized methods, using the developed algorithms guarantee the response time not in excess of 2s for the mean count rate higher than 2c/s and the controllable mean count rate error in the range of plusmn4% to plusmn10%
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