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Large Deviations for Products of Non-Identically Distributed Network Matrices With Applications to Communication-Efficient Distributed Learning and Inference

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IEEE TRANSACTIONS ON signal processing 2023年 71卷 1319-1333页

作者： Petrovic, Nemanja Bajovic, Dragana Kar, Soummya Jakovetic, Dusan Sahu, Anit Kumar Univ Novi Sad Fac Tech Sci Dept Fundamental Sci Novi Sad 21000 Serbia Univ Novi Sad Fac Tech Sci Dept Power Elect & Commun Engn Novi Sad 21000 Serbia Carnegie Mellon Univ Dept Elect & Comp Engn Pittsburgh PA 15213 USA Univ Novi Sad Fac Sci Dept Math & Informat Novi Sad 21000 Serbia Amazon Com Inc Alexa AI Pittsburgh PA 15232 USA

This paper studies products of independent but non-identically distributed random network matrices that arise as weight matrices in distributed consensus-type computation and inference procedures in peer-to-peer multi-agent networks. The non-identically distributed matrices studied in this paper model various application scenarios in which the agent communication network is time-varying, either naturally or engineered to achieve communication efficiency in computational procedures. First, under broad conditions on the statistics of the network matrix sequence, the product of the sequence is shown to converge almost surely to the consensus matrix and explicit large deviations rate of convergence are obtained. Specifically, given the admissible graph of interconnections modeling the base network topology, it is shown that the large deviations rate of consensus equals the minimum limiting value of the fluctuating graph cuts, where the edge costs are assigned through the current probabilities of the inter-agent communications. Secondly, an application of the above large deviations principle is studied in the context of distributed detection in time-varying networks with sequential observations. By adopting a consensus+innovations type distributed detection algorithm, as a by-product of this result, error exponents are obtained for the performance of distributed detection. It is shown that slow starts (slow increase) of inter-agent communication probabilities yield the same asymptotic error rate - and hence the same distributed detection performance, as if the communications were at their nominal levels from the beginning. As an important special case it is shown that when all the intermittent graph cuts have a link the probability of which increases to one, the performance of distributed detection is asymptotically optimal - i.e., equivalent to a centralized setup having access to all network data at all times.

关键词： Convergence Peer-to-peer computing Inference algorithms Electronic mail signal processing algorithms Limiting Estimation Distributed inference stochastic matrices error exponents inaccuracy rates large deviations consensus

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Adaptive Frequency Response Calibration Method for Microphone Arrays

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IEEE SENSORS JOURNAL 2020年第13期20卷 7118-7128页

作者： Wang, Rui Chen, Zhe Yin, Fuliang Dalian Univ Technol Sch Informat & Commun Engn Dalian 116024 Peoples R China

Frequency response mismatch among microphones inevitably leads to performance deterioration of signal processing algorithms of microphone arrays, especially for distributed microphone networks. An adaptive frequency response calibration method for microphone arrays based on frequency domain least mean square (FLMS) algorithm is proposed in this paper. Adaptive calibration filters are first introduced to calibrate the frequency response mismatch among microphones, which are concatenated with microphone channels. Then, the frequency response mismatch problem is formulated with a combined spectrum mean square error criterion of pairwise microphone outputs, and an unit-norm constraint is imposed to avoid undesired solutions. Finally, FLMS algorithm is used to design the calibration filter in each microphone channel. This method achieves good frequency response calibration performance even under severe ambient noise and reverberation conditions. Experimental results reveal the validity of the proposed method.

关键词： Microphone arrays Frequency response Calibration Array signal processing signal processing algorithms Sensors Frequency response calibration frequency domain least mean square algorithm microphone array

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A design and computing system for signal processing applications

A design and computing system for signal processing applicat...

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International Conference on Acoustics, Speech, and signal processing (ICASSP)

作者： H. Gethoffer K. Hoffmann A. Lenzer N. Roethe H. Waldschmidt Technische Hochule Darmstadt Darmstadt Federal Republic of Germany

A high Level signal processing system is presented consisting of the abstract signal processing language SIPROL, a translator system and a general purpose signal processor GPSP. SIPROL is derived from PASCAL including useful extensions on abstract data types. A SIPROL program is compiled into an intermediate language program and then transformed onto various target machine levels by table-driven codegeneration. The hardware modules of the GPSP are derived from the virtual machine associated to the intermediate language. The kernel feature of the system facilitates a flexible transition and migration from software to hardware with respect to the signal processing speed requirements.

关键词： signal design signal processing Hardware Virtual machining signal processing algorithms Process design Very large scale integration Program processors Kernel Guidelines

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Digital signal processing for coherent transceivers in next generation optical networks

Digital signal processing for coherent transceivers in next ...

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European Conference on Optical Communication (ECOC)

作者： C. R. S. Fludger Cisco Optical GmbH

This tutorial reviews the latest developments in Digital signal processing for coherent transceivers and their use in Next Generation Optical networks.

ISBN: (纸本)9781479930661

This tutorial reviews the latest developments in Digital signal processing for coherent transceivers and their use in Next Generation Optical networks.

关键词： Digital signal processing Modulation signal processing algorithms Optical receivers Optical signal processing Optical transmitters High-speed optical techniques

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Adaptive Parallel Optimization Design for signal processing on Multi-core and Many-core Platforms

Adaptive Parallel Optimization Design for Signal Processing ...

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International Conference on Electronics and Information Technology (EIT)

作者： Wenjun Han He Li Ga Wang Nanjing Electronic Technology Research Institute Nanjing Southeast University Nanjing University of Science and Technology of China Hefei

ISBN: (数字)9798350369151

ISBN: (纸本)9798350369168

Based on the characteristics and parallel design research of multi-core and many-core hardware platforms, this paper proposes an adaptive parallel optimization design method for signal processing on multi-core and many-core platforms. By employing a hardware platform architecture-aware approach and a multi-core segmented pipeline design, adaptive parallel optimization is achieved. The method was tested and verified using a two-stage FFT algorithm on the Phytium 2000+ platform. The test results indicate that through multiple iterations of optimization, adaptive high-performance parallel processing on multi-core and many-core platforms can be realized.

关键词： Multicore processing Pipelines signal processing algorithms Simulated annealing signal processing Parallel processing Hardware Resource management Information technology Optimization

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A preferential design approach for energy-efficient and robust implantable neural signal processing hardware

A preferential design approach for energy-efficient and robu...

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Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC)

作者： Seetharam Narasimhan Hillel J. Chiel Swarup Bhunia Department of Electrical and Computer Engineering Case Western Reserve University Cleveland OH USA Departments of Biology Neuroscience and Biomedical Engineering Case Western Reserve University Cleveland OH USA

For implantable neural interface applications, it is important to compress data and analyze spike patterns across multiple channels in real time. Such a computational task for online neural data processing requires an innovative circuit-architecture level design approach for low-power, robust and area-efficient hardware implementation. Conventional microprocessor or Digital signal processing (DSP) chips would dissipate too much power and are too large in size for an implantable system. In this paper, we propose a novel hardware design approach, referred to as ldquoPreferential Designrdquo that exploits the nature of the neural signal processing algorithm to achieve a low-voltage, robust and area-efficient implementation using nanoscale process technology. The basic idea is to isolate the critical components with respect to system performance and design them more conservatively compared to the noncritical ones. This allows aggressive voltage scaling for low power operation while ensuring robustness and area efficiency. We have applied the proposed approach to a neural signal processing algorithm using the Discrete Wavelet Transform (DWT) and observed significant improvement in power and robustness over conventional design.

关键词： signal design Energy efficiency Robustness signal processing Hardware Algorithm design and analysis Discrete wavelet transforms Digital signal processing chips signal processing algorithms Data analysis

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IF signal processing Algorithm for GPS Software Receiver

IF Signal Processing Algorithm for GPS Software Receiver

引用

Congress on Image and signal processing, CISP

作者： Zuohu Li Jinming Hao Jianwen Li Chengjun Zhang Zhengzhou Institute of Surveying and Mapping Zhengzhou China Wuhang University Wuhan China

Based on simple comparison between a conventional navigation receiver and a GNSS software receiver, a generic GNSS receiver architecture is given, which focuses on the GPS IF signal processing algorithm in the channel. According to the channel states the algorithm falls into four parts: signal acquisition, confirmation, fine frequency estimation and tracking. A frequency domain acquisition based on FFT operation is proposed, but the acquisition results need to be confirmed because of the false alarm probability. signal confirmation is formed on the basis of the conventional threshold detection method using the changes in the Doppler shifts and code phases during several consecutive sampling periods. The fine frequency estimation adopts signalspsila phase relation obtained from FFT. signal tracking is a combination of a Costas Phase Look Loop (PLL) and a non-coherent Early-Late gate delay lock loop (DLL). At the end of the paper, the results of the experiments with real GPS IF signal confirm valid operation of the proposed GPS signal processing.

关键词： signal processing algorithms Global Positioning System Satellite navigation systems Frequency estimation Tracking loops signal processing Computer architecture Frequency domain analysis Phase detection Doppler shift

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Two New Methods of Preset Time Mean Count Rate Metering Using Adaptive Digital signal processing

Two New Methods of Preset Time Mean Count Rate Metering Usin...

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Eurocon

作者： A.D. Zigic Electronics Department Vinca Institute of Nuclear Sciences Serbia

Two new methods developed to improve the classical preset time count rate meters by using the adaptive signal processing tools, are presented. An optimized detection algorithm that senses the change of the mean count rate was implemented in both methods. Three low-pass filters of various structures with adaptive parameters to implement the control of the mean count rate error were considered. An adaptation algorithm for preset time interval calculations was devised and implemented in both methods differing only in the place of its execution (before or after the low-pass filters). The simulated and realized methods, using the developed algorithms guarantee the response time not in excess of 2s for the mean count rate higher than 2c/s and the controllable mean count rate error in the range of plusmn4% to plusmn10%

关键词： Digital signal processing Low pass filters Error correction signal processing algorithms Adaptive signal processing Optimization methods Detection algorithms Adaptive filters Programmable control Adaptive control

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An architecture and a simulator for parallel signal processing

An architecture and a simulator for parallel signal processi...

引用

IEEE Southeastcon

作者： S.T. Alexandre W.E. Alexander D.S. Reeves Departments of Electrical and Computer Engineering and Computer Science North Carolina State University Raleigh NC USA

The real-time implementation of many digital signal processing (DSP) algorithms requires novel algorithm mapping methods and architectures. Some of the architectures developed thus far include data-flow systems, systolic arrays, and wavefront arrays. Ideas from these architectures are combined with the concept of block data flow processing to present the block data flow architecture (BDFA). Key features of the BDFA include direct input/output to all processors, linear data-flow, and globally asynchronous operation. Use of the BDFA for 2-D filtering is presented and analyzed. The analysis is facilitated using timing results generated by a simulator developed with the C programming language. Development of the simulator is discussed in terms of how an architecture like the BDFA can be described and simulated in C. Simulation results show that the increase in throughput with the number of processors is nearly linear.< >

关键词： signal processing signal processing algorithms Digital signal processing Array signal processing signal mapping Systolic arrays Filtering Timing Analytical models Computer languages

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Configuration Mechanism of Software Defined Chip Applied in signal processing

Configuration Mechanism of Software Defined Chip Applied in ...

引用

IEEE International Conference on Electronics and Communication Engineering (ICECE)

作者： Yu Li Hao Chen Huizhu Zhu Rongyang Wang Guiqiang Peng Shaojun Wei Leibo Liu School of Integrated Circuits Tsinghua University Beijing China China National Aeronautical Radio Electronics Research Institute Shanghai China

ISBN: (纸本)9781665487900

In order to give full play to the advantages of software defined chip hardware architecture, this paper designs a configuration mechanism of software defined chip applied in the field of signal processing. Firstly, this paper designs the configuration line execution iteration of PE (processing Element); Secondly, the iteration times of PE top layer are designed; Thirdly design the number of PEA (processing element array) top-level iterations; Finally, the implementation of matrix multiplication algorithm is used to analyze the hardware design results. Through simulation, the results show that, compared with TI c66x DSP, the clock cycle required to execute the same algorithm is reduced from 15325 to 200; The power consumption is reduced from 1092 mW to 420 mW, and the processing speed and power consumption are better than those of TI c66x DSP.

关键词： Power demand Software algorithms Key performance indicator signal processing algorithms Organizations Computer architecture Parallel processing

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