An overview is presented of a VLSI system compiler which generates highly parallel and fast processor array on a VLSI chip for general digital signal processing algorithms. In line with this overview, a description is...
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An overview is presented of a VLSI system compiler which generates highly parallel and fast processor array on a VLSI chip for general digital signal processing algorithms. In line with this overview, a description is given of a modularization and a synchronization of general digital signal processing algorithms which convert them into suitable forms for implementation by a processor array on a VLSI chip.< >
Highly optimized libraries of vector and matrix math functions, such as the Intel integrated performance primitive (IPP) libraries, can be used to quickly and economically construct high performance signalprocessing ...
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Highly optimized libraries of vector and matrix math functions, such as the Intel integrated performance primitive (IPP) libraries, can be used to quickly and economically construct high performance signalprocessing systems built up around personal computer technology. This paper describes a portable benchmarking software suite that has been developed for benchmarking the performance obtainable with IPP implementations of common signal processing algorithms, including the fast Fourier transform (FFT) and finite impulse response (FIR) filter. The results presented provide useful insights into system design choices concerning algorithms, software architecture and processors
As electricity demand increases day-by-day, power engineers strive to generate and transmit as much power as possible via the preinstalled transmission lines. Series compensation have become popular option in long tra...
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ISBN:
(数字)9781665474979
ISBN:
(纸本)9781665474986
As electricity demand increases day-by-day, power engineers strive to generate and transmit as much power as possible via the preinstalled transmission lines. Series compensation have become popular option in long transmission lines worldwide as it increases the transmission capacity of the system. But due to the use of series compensation (capacitors), transmission line protection becomes complex due to various changes in the line parameters, looking from the point of relay installation such as change in impedance, current and voltage inversion. Existing protection concepts will have to be modified to accommodate these issues. A protection algorithm (PA) based on three signalprocessing techniques is proposed in this paper for identification and categorization of faults in series compensated electrical transmission network. Study has been done and validated on MATLAB/Simulink environment.
In the framework of an on-going R&D program on CZT detectors for astrophysical applications, we have started a study to address peculiar problems affecting this kind of detectors (e.g. response dependent on the in...
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In the framework of an on-going R&D program on CZT detectors for astrophysical applications, we have started a study to address peculiar problems affecting this kind of detectors (e.g. response dependent on the interaction depth and multiple hit events) using a digital approach: the output of an analog front end chain based on a fast charge preamplifier, which preserves the shape of the signal as generated by the detector, sampled with a fast ADC, is processed to extract information to improve the performance, in particular the energy resolution. In this context, we have developed a flexible readout electronics to be used to characterize CZT array and test digital processingalgorithms. The system includes analog front-end electronics, digital signalprocessing based on an FPGA board, and a Gb Ethernet interface for PC-based data acquisition. Current scheme allows the readout of a 4×4 pixels, which allows us to test the algorithms even for multi-pixels events and checking cross-talk effects. However, the system has been designed to be easily extended to an higher number of pixels by duplicating the Analog Front End board. Up to 4 AFEE boards can be managed by the system (thus supporting 64 channels, allowing a 16×16 array to be readout). Performance of the system with a commercial 4×4 pixels CZT (eV-products) will be reported in the paper.
The task of programming concurrent systems is substantially more difficult than the task of programming sequential systems with respect to both correctness and efficiency. The tendency in development of embedded, DSP ...
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The task of programming concurrent systems is substantially more difficult than the task of programming sequential systems with respect to both correctness and efficiency. The tendency in development of embedded, DSP systems and processors are shifting to multi core and multiprocessor setups as well. The problem of easy concurrency and algorithm development is an important for embedded and DSP systems as well. The goal of this paper is to define and present a high level language that allows description and development of signal processing algorithms. With the usage of a domain specific language, we can create compact and easy to understand definition of algorithms. In the paper the authors present the advantages granted by DSL for DSP applications. The created definitions are hardware independent can be executed and functionally verified. Efficient code can be generated for various targets without porting. The design of the presented DSL allows code generation for multi-core targets in case of computing-intensive algorithms, code generation for multiple streams, threads. Code reuse is supported by merging, re-grouping, and splitting of algorithms and groups of algorithms.
A switched-current integrator configuration with greatly improved sensitivity to transistor mismatch is described. Forward-Euler, backward-Euler, and bilinear-z mappings are described, as well as an integrator which r...
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A switched-current integrator configuration with greatly improved sensitivity to transistor mismatch is described. Forward-Euler, backward-Euler, and bilinear-z mappings are described, as well as an integrator which responds to the derivative of the input current. An universal integrator configuration which performs an identical algorithm to a well-known switched-capacitor universal integrator is developed. It can be used to translate known switched-capacitor filter topologies into switched-current counterparts, as is demonstrated by the simulation of a sixth-order low-pass filter.< >
Application of Compressive Sensing (CS) in Linear Frequency Modulation Continuous Wave (LFMCW) radar had been investigated and proved by the authors in [8]. An approach, namely architecture 1, had been evaluated by th...
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ISBN:
(纸本)9781509008643
Application of Compressive Sensing (CS) in Linear Frequency Modulation Continuous Wave (LFMCW) radar had been investigated and proved by the authors in [8]. An approach, namely architecture 1, had been evaluated by the authors in [11] which dependent mainly on applying CS in range direction. But there is a limitation on the number of the detected targets in range. So, in the present paper, a new approach for applying CS in LFMCW radar signalprocessing, namely architecture 2, is introduced depends on apply CS in azimuth direction (range sweeps). The reduction in range sweeps is performed using a Pseudo Random (PN) sequence in Azimuth according to the required reduction ratio in range sweeps. The information of the received radar signal (target range and speed) are reconstructed by the use of Complex Approximate Message Passing (CAMP) reconstruction algorithm. Performance of the proposed LFMCW radar signal processors based on CS (architecture2) is evaluated and compared to that of both the traditional one based on Fast Fourier Transform (FFT)) and architecture 1 from points of view of detection performance through Receiver Operating Characteristics (ROC) curves, resolution performance and hardware complexity. The proposed approach (architecture 2) is designed and implemented using Field Programmable Gate Array (FPGA).
The algorithm of constructing of weight coefficients that guarantees receiving the source signal getting into the main maximum of directive pattern and suppressing other sources signals is investigated. Basing on the ...
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The algorithm of constructing of weight coefficients that guarantees receiving the source signal getting into the main maximum of directive pattern and suppressing other sources signals is investigated. Basing on the analytic form of the inverse covariance matrix for signals the estimations of the possible meanings of the signal/noise relation depending on the parameters of antenna system and signals (number and step of radiator displacement, receiving signals covariance degree) are found. The results of mathematical modelling of signalprocessing based on the algorithm are given.
We present a methodology and design flow for signalprocessing application specific integrated circuit macro-cells. The key features of the methodology are the mastering the complexity of design, the increasing of reu...
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We present a methodology and design flow for signalprocessing application specific integrated circuit macro-cells. The key features of the methodology are the mastering the complexity of design, the increasing of reuse factor and the early error detection. It takes advantages of a derivative designs, a signalprocessing modularity, generic modeling and combines both levels of abstraction, in order to produce an efficient architecture. The flow includes a fast verification platform that drives both algorithm and architecture validation in an efficient way. We illustrate the effectiveness of the proposed methodology by a significant industrial application. Experimental design results indicate strong advantages of the proposed schemes.
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