By establishing a singleparitycheck relationship between convolutional codewords, a concatenated code, termed singleparitycheck convolutional code (SPC-CC), is proposed. By jointly en/decoding the SPC and CC, as w...
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ISBN:
(纸本)9780738124766
By establishing a singleparitycheck relationship between convolutional codewords, a concatenated code, termed singleparitycheck convolutional code (SPC-CC), is proposed. By jointly en/decoding the SPC and CC, as well as carefully allocating redundant information between the pair, we can improve BER more promptly during iterative decoding. Each codeword in SPC-CC consists of only one SISO decoder, which generates one extrinsic information. The key is to simulate another using extrinsic information from other decoders. Then iteratively feed back extrinsic information to each other in a manner similar to a Turbo engine. We design en/decoding scheme of the SPC-CC, and then analyze its performance and complexity. Simulation results show that SPC-CC can effectively improve communication reliability with a moderate complexity. In addition, thanks to SPC code, SPC-CC can correct packet erasures due to fading or interference.
Highly Reliable Communication (HRC) is an emerging paradigm for meeting the quality of service requirements of new applications such as intelligent vehicle networking and industrial Internet. HRC brings challenges to ...
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Highly Reliable Communication (HRC) is an emerging paradigm for meeting the quality of service requirements of new applications such as intelligent vehicle networking and industrial Internet. HRC brings challenges to channel coding and multiple access. Various channel coding techniques have been proposed to improve reliability, but often suffer from limited reliability and high decoding complexity. This work presents a double serial concatenated code using CRC-aided error correction, abbreviated as (DSCEC)-E-3, to improve reliability and reduce complexity. The encoding scheme is a double serial concatenated code, with the cascade of a set of CRC encoders, a linear block encoder, a series of interleavers, and a set of convolutional encoders. The decoding scheme consists of two modules: (i) decoding of serial concatenated codes, which includes the decoding of singleparitycheck convolutional code (SPC-CC) and the decoding of Reed-Solomon convolutional code (RSCC) for intra-block error correction at the physical layer to control BER;(H) decoding of CRC-aided linear error correction, which can effectively identify, locate and correct error bits at the inter-block level to solve the problem of block loss caused by residual errors at the physical layer. Simulation results show that the joint scheme can effectively improve communication reliability while reducing complexity.
The areal density growth of magnetic recording systems is fast approaching the superparamagnetic limit for conventional magnetic disks. This is due to the increasing demand for high data storage capacity. Two-dimensio...
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The areal density growth of magnetic recording systems is fast approaching the superparamagnetic limit for conventional magnetic disks. This is due to the increasing demand for high data storage capacity. Two-dimensional Magnetic Recording (TDMR) is a new technology aimed at increasing the areal density of magnetic recording systems beyond the limit of current disk technology using conventional disk media. However, it relies on advanced coding and signal processing techniques to achieve areal density gains. Current state of the art signal processing for TDMR channel employed iterative decoding with Low Density paritycheck (LDPC) codes, coupled with 2D equalisers and full 2D Maximum Likelihood (ML) detectors. The shortcoming of these algorithms is their computation complexity especially with regards to the ML detectors which is exponential with respect to the number of bits involved. Therefore, robust low-complexity coding, equalisation and detection algorithms are crucial for successful future deployment of the TDMR scheme. This present work is aimed at finding efficient and low-complexity coding, equalisation, detection and decoding techniques for improving the performance of TDMR channel and magnetic recording channel in general. A forward error correction (FEC) scheme of two concatenated singleparity bit systems along track separated by an interleaver has been presented for channel with perpendicular magnetic recording (PMR) media. Joint detection decoding algorithm using constrained MAP detector for simultaneous detection and decoding of data with singleparity bit system has been proposed. It is shown that using the proposed FEC scheme with the constrained MAP detector/decoder can achieve a gain of up to 3dB over un-coded MAP decoder for 1D interference channel. A further gain of 1.5 dB was achieved by concatenating two interleavers with extra parity bit when data density along track is high. The use of single bit paritycode as a run length limited code as w
Some proposed high speed wireline communications make use of an ADC front end to allow a feedforward equalizer (FFE) to compensate for the frequency dependent loss of the channel. High precision ADCs are expensive in ...
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ISBN:
(纸本)9781479970889
Some proposed high speed wireline communications make use of an ADC front end to allow a feedforward equalizer (FFE) to compensate for the frequency dependent loss of the channel. High precision ADCs are expensive in terms of power. The FFE block performs multiplication and addition operations at high speed and further increases the power consumption. This paper proposes a simple forward error correction method by which the ADC resolution and the equalizer complexity can be reduced. A single parity check code implemented together with a threshold detector can provide single error correction capability. With this error correction capability, the number of taps required in the FFE block is shown to be reduced to 3 taps from 6 taps for a channel with 15dB insertion loss at 5GHz frequency with the data rate being 20Gb/s. The effective number of bits (ENOB) required from the ADC is also shown to reduce to about 3.5 bits from 6 bits. The high rate of the code and the very simple decoder architecture make this error correction mechanism well suited for the wireline application.
In this paper, both performance and complexity aspects of two-dimensional singleparitycheck turbo product codes (I-SPC-TPC) are investigated. Based on the proposed I-SPC-TPC coding scheme, a parallel decoding struct...
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In this paper, both performance and complexity aspects of two-dimensional singleparitycheck turbo product codes (I-SPC-TPC) are investigated. Based on the proposed I-SPC-TPC coding scheme, a parallel decoding structure is developed to increase the decoding throughput with minor performance degradation compared with the serial structure. For both decoding architectures, a new helical interleaver is constructed to further improve the coding gain. In terms of decoding algorithm, the extremely simple Sign-Min decoding is alternatively derived with only three additions needed to compute each bit's extrinsic information. For performance evaluation, (16, 14, 2)(2) singleparitycheck turbo product code with code rate 0.766 over AWGN channel using QPSK modulation is considered. The simulation results using Sign-Min decoding show that it can achieve bit-error-rate of 10(-5) at signal-to-noise ratio of 3.8 dB with 8 iterations. Compared to the same rate and codeword length turbo product code composed of extended Hamming codes, the considered scheme can achieve similar performance with much less complexity. Important implementation issues such as the finite precision analysis, efficient sorting circuit design and interleaver memory management are also presented.
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