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Exploring System Availability During software-based self-testing of Multi-core CPUs

JOURNAL OF ELECTRONIC testing-THEORY AND APPLICATIONS 2018年第1期34卷 67-81页

作者： Skitsas, Michael A. Nicopoulos, Chrysostomos A. Michael, Maria K. KIOS Res & Innovat Ctr Excellence Nicosia Cyprus Univ Cyprus Dept Elect & Comp Engn Nicosia Cyprus

As technology scales, the increased vulnerability of modern systems due to unreliable components becomes a major problem in the era of multi-/many-core architectures. Recently, several on-line testing techniques have been proposed, aiming towards error detection of wear-out/aging-related defects that can appear during the lifetime of a system. In this work, firstly we investigate the relation between system test latency and test-time overhead in multi-/many-core systems with shared Last-Level Cache (LLC) for periodic software-based self-testing (SBST), under different test scheduling policies. Secondly, we propose a new methodology aiming to reduce the extra overhead related to testing that is incurred as the system scales up (i.e., the number of on-chip cores increases). The investigated scheduling policies primarily vary the number of cores concurrently under test in the overall system test session. Our extensive, workload-driven dynamic exploration reveals that there is an inverse relationship between the two test measures;as the number of cores concurrently under test increases, system test latency decreases, but at the cost of significantly increased test time, which sacrifices system availability for the actual workloads. Under given system test latency constraints, which dictate the recovery time in the event of error detection, our exploration framework identifies the scheduling policy under which the overall test-time overhead is minimized and, hence, system availability is maximized. For the evaluation of the proposed techniques, multi-/many-core systems consisting of 16 and 64 cores are explored in a full-system, execution-driven simulation framework running multi-threaded PARSEC workloads.

关键词： On-line testing software-based self-testing System availability

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Exploration of System Availability During software-based self-testing in Many-core Systems under Test Latency Constraints 27

Exploration of System Availability During Software-Based Sel...

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IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)

作者： Skitsas, Michael A. Nicopoulos, Chrysostomos A. Michael, Maria K. Univ Cyprus KIOS Res Ctr Nicosia Cyprus Univ Cyprus Dept ECE Nicosia Cyprus

ISBN: (纸本)9781479961559

As technology scales, the increased vulnerability of modern systems due to unreliable components becomes a major problem in the era of multi-/many-core architectures. Recently, several on-line testing techniques have been proposed, aiming towards error detection of wear-out/aging-related defects that can appear during the lifetime of a system. In this work, we investigate the relation between system test latency and test-time overhead in multi-/many-core systems with shared Last-Level Cache (LLC) for periodic software-based self-testing (SBST), under different test scheduling policies. The investigated scheduling policies primarily vary the number of cores concurrently under test in the overall system testing session. Our extensive, workload-driven dynamic exploration reveals that there is an inverse relation between the two test measures;as the number of cores concurrently under test increases, system test latency decreases, but at the cost of significantly increased test time, which sacrifices system availability for running normal workloads. Under given system test latency constraints, which should be utilized in order to be able to control system recovery time in the event of an error detection, our exploration framework identifies the scheduling policy under which overall test time overhead is minimized and, hence, system availability is maximized Without any loss of generality, a 16-core system is explored in a full-system, execution-driven simulation framework running multi-threaded PARSEC workloads [1].

关键词： automatic testing cache storage error detection multiprocessing systems program testing 16-core system LLC SBST last level cache many-core systems multicore architectures multithreaded PARSEC workloads software-based self-testing system availability test latency constraints test scheduling policy testtime overhead wear-out-aging-related defects workload-driven dynamic exploration Availability Benchmark testing Measurement Optimization Processor scheduling Scheduling Error detection Automatic testing Benchmark testing Multiprocessing systems scheduling of multiprocessor program testing cache storage System testing Exploration

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HASTI: hardware-assisted functional testing of embedded processors in idle times

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IET COMPUTERS AND DIGITAL TECHNIQUES 2019年第3期13卷 198-205页

作者： Kamran, Arezoo Razi Univ Kermanshah Iran

In the past decades, software-based self-testing (SBST) which is testing of a processing core using its native instructions has attracted much attention. However, efficient SBST of a processing core which is deeply embedded in a multicore architecture is still an open issue. In this study, inspiring from built-in self-test methods, the authors place several number of hardware test components next to the processing cores in order to overcome existing SBST challenges. These test components facilitate quick testing of embedded cores by providing several mechanisms such as virtual fetch, virtual jump, fake load & store, and segmented test application. In order to enable segmented test application, they propose the concept of test snippet and a test snippet generation approach. The result is the capability of testing embedded cores in short idle times leading to efficient online testing of the cores with zero performance overhead. The authors' results show that their test snippet generation approach not only leads to the production of test snippets which are properly fitted the proposed test architecture but also its final fault coverage is comparable and even a little better than the fault coverage of the best existing methods.

关键词： embedded systems built-in self test program testing microprocessor chips multiprocessing systems integrated circuit testing hardware-assisted functional testing embedded processors software-based self-testing hardware test components segmented test application test snippet generation approach efficient online testing test architecture SBST embedded core testing HASTI multicore architecture built-in self-test methods short idle times zero performance overhead

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Improved and Evolutionary software based scheduling Technique for Embedded Cores 2

Improved and Evolutionary Software based scheduling Techniqu...

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2nd International Conference for Convergence in Technology (I2CT)

作者： Puranik, Vishal G. Jha, Chanakya Kumar Dr BAMU Aurangabad Maharashtra India Savitribai Phule Pune Univ Dept Elect & Telecommun Pune Maharashtra India

ISBN: (纸本)9781509043071

Fault detection or coverage measurement with the help of Built-in self-test (BIST) is a technique using test patterns employing embedded hardware components which generates the response and the components which analyzes these responses. This method does not require any external tester as fault testing is performed at the speed in line with the testee. As a result of this, it faces the difficulties like Area overhead, Performance penalties. The design time and efforts needed are more. By exploiting programmability and using on-chip resources a new technique called software-based self-test (SBST) scheduling is introduced which excludes the requirement as in previous methods.

关键词： software-based self-testing self-Test programs Fault detection RISC MIPS Processor

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DaemonGuard: Enabling O/S-Orchestrated Fine-Grained software-based Selective-testing in Multi-/Many-Core Microprocessors

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IEEE TRANSACTIONS ON COMPUTERS 2016年第5期65卷 1453-1466页

作者： Skitsas, Michael A. Nicopoulos, Chrysostomos A. Michael, Maria K. Univ Cyprus KIOS Res Ctr CY-1678 Nicosia Cyprus Univ Cyprus Dept Elect & Comp Engn ECE CY-1678 Nicosia Cyprus

As technology scales deep into the sub-micron regime, transistors become less reliable. Future systems are widely predicted to suffer from considerable aging and wear-out effects. This ominous threat has urged system designers to develop effective run-time testing methodologies that can monitor and assess the system's health. In thiswork, we investigate the potential of online software-based functional testing at the granularity of individual microprocessor core components in multi-/many-core systems. While existing techniques monolithically test the entire core, our approach aims to reduce testing time by avoiding the over-testing of under-utilized units. To facilitate fine-grained testing, we introduce DaemonGuard, a framework that enables the real-time observation of individual sub-core modules and performs on-demand selective testing of only the modules that have recently been stressed. Moreover, we investigate the impact of the cache hierarchy on the testing process and we develop a cache-aware selective testing methodology that significantly expedites the execution of memory-intensive test programs. The monitoring and test-initiation process is orchestrated by a transparent, minimally-intrusive, and lightweight operating system process that observes the utilization of individual datapath components at run-time. We performa series of experiments using a full-system, execution-driven simulation framework running a commodity operating system, real multi-threaded workloads, and test programs. Our results indicate that operating-system-assisted selective testing at the sub-core level leads to substantial savings in testing time and very low impact on system performance. Additionally, the cache-aware testing technique is shown to be very effective in exploiting the memory hierarchy to further minimize the testing time.

关键词： On-line testing software-based self-testing system reliability adaptive testing

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software-based self-testing of embedded processors

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IEEE TRANSACTIONS ON COMPUTERS 2005年第4期54卷 461-475页

作者： Kranitis, N Paschalis, A Gizopoulos, D Xenoulis, G Univ Athens Dept Informat & Telecommun Athens 15784 Greece Univ Piraeus Dept Informat Piraeus 18534 Greece

Embedded processor testing techniques based on the execution of self-test programs have been recently proposed as an effective alternative to classic external tester-based testing and pure hardware built-in self-test (BIST) approaches. software-based self-testing is a nonintrusive testing approach and provides at-speed testing capability without any hardware or performance overheads. In this paper, we first present a high-level, functional component-oriented, software-based self-testing methodology for embedded processors. The proposed methodology aims at high structural fault coverage with low test development and test application cost. Then, we validate the effectiveness of the proposed methodology as a low-cost alternative over structural software-based self-testing methodologies based on automatic test pattern generation and pseudorandom testing. Finally, we demonstrate the effectiveness and efficiency of the proposed methodology by completely applying it on two different processor implementations of a popular RISC instruction set architecture including several gate-level implementations.

关键词： embedded processors processor self-testing software-based self-testing low-cost testing

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Exploiting Thread-Level Parallelism in Functional self-testing of CMT Processors

Exploiting Thread-Level Parallelism in Functional Self-Testi...

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14th IEEE European Test Symposium (EST 2009)

作者： Apostolakis, Andreas Psarakis, Mihalis Gizopoulos, Dimitris Paschalis, Antonis Parulkar, Ishwar Univ Piraeus Dept Informat Comp Syst Lab Piraeus Greece Univ Athens Dept Informat & Telecom GR-10679 Athens Greece Sun Microsyst Santa Clara CA USA

ISBN: (纸本)9780769537030

Major microprocessor vendors have integrated functional software-based self-testing in their manufacturing test flows during the last decade. Functional self-testing is performed by test programs that the processor executes at-speed from on-chip memory. Multiprocessors and multithreaded architectures are constantly becoming the typical general-purpose computing paradigm, and thus the various existing uniprocessor functional self-testing schemes must be adopted and adjusted to meet the testing requirements of complex multiprocessors. A major challenge in porting a functional self-testing approach from the uniprocessor to the multiprocessor case is to take advantage of the inherent execution parallelism offered by the multiple cores and the multiple threads in order to reduce test execution time. In this paper, we study the application of functional self-testing to chip multithreaded (CMT) processors. We propose a method that exploits thread-level parallelism (TLP) to speed up the execution of self-test routines in every physical core of a multiprocessor chip. The proposed method effectively splits the self-test routines into shorter ones, assigns the new routines to the hardware threads of the core and schedules their execution in order to minimize the core idle intervals due to cache misses or long latency operations and maximize the utilization of core computing resources. We demonstrate our method in the open-source CMT multiprocessor model, Sun's OpenSPARC T1, which contains eight CPU cores, each one supporting four hardware threads. Our experimental results show a self-test execution speedup of more than three times compared to the single thread execution.

关键词： Chip multithreading multiprocessors microprocessor testing functional self-testing software-based self-testing test time optimization

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A New Methodology for the Test of SoCs and for Analyzing Elusive Failures

A New Methodology for the Test of SoCs and for Analyzing Elu...

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9th International Workshop on Microprocessor Test and Verification

作者： Weiss, Alexander Hochberger, Christian Accem GmbH & Co KG Flintsbach Germany Tech Univ Dresden Dept Comp Sci Dresden Germany

ISBN: (纸本)9780769535814

The increasing complexity of SoCs in form of more complex architecture design, and smaller structures qualifies lest procedures and failure analysis as one of the key skills if the semiconductor industry. In this contribution we show a new SoC test methodology which significantly increases the lest coverage of a SoC. The integrated system integrity control functionality of the hidICE approach observes a SoC core and is able to detect irregularities in comparison to a reference system. In case of a failure detection an exhaustive trace is available which helps to identify the root cause. Especially in multi-core systems the interference between different subsystems can be tested under real operating conditions. Also the effort to identify and analyze elusive failures will be reduced.

关键词： Failure analysis Fault diagnosis Fault analysis Embedded processor Microcontroller SoC Built-in self-test BIST software-based self-testing SBST Observability hidICE

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Dynamic scheduling of test routines for efficient online self-testing of embedded microprocessors

Dynamic scheduling of test routines for efficient online sel...

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14th IEEE International On-Line testing Symposium

作者： Bartzoudis, Nikolaos Tantsios, Vasileios McDonald-Maier, Klaus CTTC Ave Canal Olimp S-N Barcelona 08860 Spain Univ Essex Dept Comp & Elect Syst Colchester CO4 3SQ Essex England

ISBN: (纸本)9780769532646

This paper presents a self-testing framework targeting the LEON3 embedded microprocessor with built-in test-scheduling features. The proposed design exploits existing postproduction test sets, designed for software-based testing of embedded microprocessors. The framework also includes a constraint-based approach of test-routine scheduling. The initial results show that the test execution time could be dynamically scaled by the test selection algorithm.

关键词： online testing software-based self-testing test scheduling resource-aware testing

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Low-cost, on-line self-testing of processor cores based on embedded software routines

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MICROELECTRONICS JOURNAL 2004年第5期35卷 443-449页

作者： Gizopoulos, D Univ Piraeus Dept Informat Piraeus Greece

On-line testing for complex system-on-chip architectures requires a synergy of concurrent and non-concurrent fault detection mechanisms. While concurrent fault detection is mainly achieved by hardware or software redundancy, like duplication, non-concurrent fault detection, particularly useful for periodic testing, is usually achieved through hardware-based self-test. software-based self-test has been recently proposed as an effective alternative to hardware-based self-test allowing at-speed testing while eliminating area, performance and power consumption overheads. In this paper, we investigate the applicability of software-based self-test to non-concurrent on-line testing of embedded processor cores and define, for the first time, the corresponding requirements. Low-cost, in-field testing requirements, particularly small test execution time and low power consumption guide the development of self-test routines. We show how self-test programs with a limited number of memory references and based on compact test routines provide an efficient low-cost on-line test strategy for an RISC processor core. (C) 2004 Elsevier Ltd. All rights reserved.

关键词： on-line testing processor testing self-testing software-based self-testing low-cost testing

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