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18th International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)

作者： Chen, Renyu Choi, Woosung Schmidt, Alexander Lee, Keun-Ho Park, Youngkwan Samsung Semicond Inc Device Lab San Jose CA 95134 USA Samsung Elect Semicond R&D Ctr Hwasung Si Gyeonggi Do South Korea

ISBN: (纸本)9781467357333

We have developed a new kinetic lattice Monte Carlo modeling framework for Si/Ge selective epitaxial growth based on neighbor binding interactions within the third-nearest-neighbor range of the diamond lattice. We find that first- and second-nearest-neighbor interactions contribute significantly to the faceting between {100} and {111}, while the third-nearest-neighbor interaction is the cause of {311} facet formation. The second-nearest-neighbor interaction also facilitates lateral growth and island formation within a plane. The simulated growth kinetics and shapes are in good agreement with experimental data.

关键词： selective epitaxial growth kinetic lattice Monte Carlo source-drain engineering

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Scaling considerations for sub-90 nm split-gate flash memory cells

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IET CIRCUITS DEVICES & SYSTEMS 2008年第1期2卷 144-150页

作者： Saha, S. K. DSM Solut Inc Los Gatos CA 95032 USA Synopsys Inc Mountain View CA 94043 USA

A systematic methodology is presented to scale split-gate (SG) flash memory cells in the sub-90 nm regime within the presently known scaling constraints of flash memory. The numerical device simulation results show that the high performance sub-90 nm NOR-type SG cells can be achieved by a suitable channel and source-drain engineering. An asymmetric channel doping profile along with ultra-shallow source-drain junctions was used to achieve the target drain programming voltage (V-sp) for an efficient cell programming while keeping the cell breakdown voltage, BV > V-sp, with tolerable leakage currents. The study shows that with properly optimised technology parameters, 65 nm SG-NOR flash memory can be achieved with an adequate cell read current, a tolerable programmed cell leakage current at the read condition and efficient write and erase times.

关键词： source-drain junctions suitable channel source-drain engineering asymmetric channel doping profile programming voltage cell breakdown voltage programmed cell leakage current scale split-gate flash memory cells logic gates leakage currents flash memories cell programming SG-NOR flash memory NOR-type SG cells

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Mainstream rapid thermal processing for source-drain engineering from first applications to latest results

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MATERIALS SCIENCE AND engineering B-SOLID STATE MATERIALS FOR ADVANCED TECHNOLOGY 2004年第12期114卷 141-150页

作者： Niess, J Paul, S Buschbaum, S Schmid, P Lerch, W Mattson Thermal Prod GmbH D-89160 Dornstadt Germany

Rapid thermal processing (RTP) technology has been commercially available in the semiconductor industry for about 30 years. Already in 1957, e.g., a solar furnace with a parabolic Al reflector was designed. Despite this, it took several decades for RTP of semiconductors to penetrate the market. Over the last decade, RTP has become a mature application. As a replacement of standard furnaces, it provides outstanding ambient control and very short heating cycles with the highest ramp rates for promotion of desired processes such as implant activation, silicide formation or oxide growth while suppressing unintended processes like diffusion or surface degradation. In the field of ultra-shallow junction (USJ) formation, which is necessary to avoid short channel effects arising during continued scaling of CMOS devices, RTP is indispensable. With the introduction of CoSi2 as the source-drain contact material and its transition to NiSi for future technology nodes, RTP delivers unique benefits in terms of ambient control and single wafer processing capability. In the current paper, we will present the development and potential of RTP throughout this era and show latest results in USJ annealing as well as source-drain contact formation down to the 90 and 65 nm technology node of the ITRS2003, respectively. (C) 2004 Elsevier B.V. All rights reserved.

关键词： rapid thermal processing source-drain engineering applications application nickel silicide ultra-shallow junction formation

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Mainstream rapid thermal processing for source-drain engineering from first applications to latest results

Mainstream rapid thermal processing for source-drain enginee...

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Symposium on Material Science Issues in Advanced CMOS source-drain engineering held at the E-MRS 2004 Spring Meeting

作者： Niess, J Paul, S Buschbaum, S Schmid, P Lerch, W Mattson Thermal Prod GmbH D-89160 Dornstadt Germany

关键词： rapid thermal processing source-drain engineering applications application nickel silicide ultra-shallow junction formation

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Scaling issues for analogue circuits using Double Gate SOI transistors

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SOLID-STATE ELECTRONICS 2007年第2期51卷 320-327页

作者： Lim, Tao Chuan Armstrong, G. Alastair Queens Univ Belfast Sch Elect & Elect Engn NISRC Belfast BT9 5AH Antrim North Ireland

This work presents a systematic analysis on the impact of source-drain engineering using gate "non-overlapped" on the RF performance of nano-scaled fully depleted Double Gate SOI transistors, when used in the design of a typical two stage Operational Transconductance Amplifier (OTA). It is evident that for a gate length less than 40 nm, the incorporation of optimal source-drain engineering requiring a spacer length, which may exceed the length of the gate, is particularly beneficial in analogue applications. Lengthening the spacer reduces gate capacitance in the weak/moderate inversion region more than transconductance, improving cut-off frequency f(T). This improvement is particularly significant in a circuit application where an optimal spacer of 1.5 times the gate length is proposed. This gate under-lapped concept with extended spacer can also significantly enhance DC gain of the OTA, by increasing the Early Voltage, while maximising the transconductance to current ratio in the weak to moderate inversion, close to threshold voltage. With optimally designed devices, the sensitivity of OTA circuit performance to doping profile is shown to be relatively low. (c) 2007 Elsevier Ltd. All rights reserved.

关键词： Double Gate SOI operational transconductance amplifier source-drain engineering gate under-lapped spacer length MixedMode simulation unity gain bandwidth early voltage transconductance to drain current ratio

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CMOS technology for MS/RF SoC

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IEEE TRANSACTIONS ON ELECTRON DEVICES 2003年第3期50卷 557-566页

作者： Diaz, CH Tang, DD Sun, J Taiwan Semicond Mfg Co Device Engn Div R&D Hsinchu 300 Taiwan Taiwan Semicond Mfg Co Exploratory Res R&D Hsinchu 300 Taiwan Taiwan Semicond Mfg Co Log Technol Div R&D Hsinchu 300 Taiwan

Accelerated scaling of CMOS technology has contributed to remove otherwise fundamental barriers preempting its widespread application to mixed-signal/radio-frequency (MS/RF) segments. Improvements in device speed, matching, and minimum noise figure are all consistent with fundamental scaling trends. Other figures-of-merit such as linearity and 1/f noise do not scale favorably but are not considered to be roadblocks when viewed from a circuit design perspective. Furthermore, interconnect architectural scaling trends in logic technology have facilitated improvements in passive-component performance metrics. These improvements compounded with innovations in circuit design have made CMOS technology the primary choice for cost driven MS/RF applications. This paper reviews active and passive elements of CMOS MS/RF system-on-chip (SoC) technology from scaling perspective. The paper also discusses the implications that physical phenomena such as mechanical stress and gate leakage as well as gate patterning have on technology definition and characterization.

关键词： 1/f noise analog analog CMOS CMOS RF CMOS system-on-chip (SoC) CMOS technology device isolation gate dielectric gate dielectric direct tunneling gate patterning integrated capacitors integrated inductors integrated resistors fine-edge roughness (LER) matching mechanical stress in MOS devices mixed-signal (MS) mixed-signal/radio-frequency (MS/RF) noise isolation passive elements source-drain engineering system-on-chip (SoC)

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