A systematic methodology is presented to scale split-gate (SG) flash memory cells in the sub-90 nm regime within the presently known scaling constraints of flash memory. The numerical device simulation results show th...
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A systematic methodology is presented to scale split-gate (SG) flash memory cells in the sub-90 nm regime within the presently known scaling constraints of flash memory. The numerical device simulation results show that the high performance sub-90 nm NOR-type SG cells can be achieved by a suitable channel and source-drain engineering. An asymmetric channel doping profile along with ultra-shallow source-drain junctions was used to achieve the target drain programming voltage (V-sp) for an efficient cell programming while keeping the cell breakdown voltage, BV > V-sp, with tolerable leakage currents. The study shows that with properly optimised technology parameters, 65 nm SG-NOR flash memory can be achieved with an adequate cell read current, a tolerable programmed cell leakage current at the read condition and efficient write and erase times.
The embedded NOR-type Non Volatile Memory (eNVM) cell is characterized by many figures of merit. Of particular interest are the programming efficiency (PE), defined as the electron gate-to-drain current ratio (Ig/Id) ...
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ISBN:
(纸本)9781424493845
The embedded NOR-type Non Volatile Memory (eNVM) cell is characterized by many figures of merit. Of particular interest are the programming efficiency (PE), defined as the electron gate-to-drain current ratio (Ig/Id) during programming, and the drain disturb current (DDC), defined as the hole gate current Igh during drain disturb (Fig. 1). eNVM gate-length scaling has brought shallower and steeper source/drain (S/D) junctions enabling not only higher PE but also increased DDC, the latter yielding to potential reliability issues. Therefore, in the spirit of a compromise in channel/LDD implant conditions is here presented, showing a trade-off between electron and hole injection during programming and drain disturb phases, respectively.
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