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Domain-specific acceleration and auto-parallelization of legacy scientific code in FORTRAN 77 using source-to-source compilation

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COMPUTERS & FLUIDS 2018年 173卷 1-5页

作者： Vanderbauwhede, Wim Davidson, Gavin Univ Glasgow Sch Comp Sci Glasgow Lanark Scotland

Massively parallel accelerators such as GPGPUs, manycores and FPGAs represent a powerful and affordable tool for scientists who look to speed up simulations of complex systems. However, porting code to such devices requires a detailed understanding of heterogeneous programming tools and effective strategies for parallelization. In this paper we present a source to source compilation approach with whole-program analysis to automatically transform single-threaded FORTRAN 77 legacy code into OpenCL-accelerated programs with parallelized kernels. The main contributions of our work are: (1) whole-source refactoring to allow any subroutine in the code to be offloaded to an accelerator. (2) Minimization of the data transfer between the host and the accelerator by eliminating redundant transfers. (3) Pragmatic auto-parallelization of the code to be offloaded to the accelerator by identification of parallelizable maps and reductions. We have validated the code transformation performance of the compiler on the NIST FORTRAN 78 test suite and several real-world codes: the Large Eddy Simulator for Urban Flows, a high-resolution turbulent flow model;the shallow water component of the ocean model Gmodel;the Linear Baroclinic Model, an atmospheric climate model and Flexpart-WRF, a particle dispersion simulator. The automatic parallelization component has been tested on as 2-D Shallow Water model (2DSW) and on the Large Eddy Simulator for Urban Flows (UFLES) and produces a complete OpenCL-enabled code base. The fully OpenCL-accelerated versions of the 2DSW and the UFLES are resp. 9x and 20x faster on GPU than the original code on CPU, in both cases this is the same performance as manually ported code. (C) 2018 The Authors. Published by Elsevier Ltd.

关键词： Fortran GPGPU OpenCL source-to-source compilation Auto-parallelization Acceleration

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Incremental Banerjee test conditions committing for robust parallelization framework

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TURKISH JOURNAL OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCES 2018年第5期26卷 2595-2604页

作者： Debbi, Aimad Eddine Bakhti, Haddi Ferhat Abbas Univ Fac Technol Dept Elect Setif Algeria Mohamed Boudhiaf Univ Fac Math & Informat Dept Comp Sci Msila Algeria

This paper describes the design of an automatic parallelization framework. The kernel supplied at its front end was suggested as an instrument for parallel potential assessment. It was used to measure the maximum achievable speedups in the major set of the CHStone benchmark suite programs. In such framework, we suggested the liberation of parallelism incrementally. We proposed a data dependency heuristic-based transformation method to make true dependences dissociation. We generated an internal representation (IR2), where the Banerjee test conditions are met. Two among three of Banerjee test conditions came to be committed. In shared memory many/multicore platforms, the third condition could be satisfied by privatization. We would be able to choose the safe and the opportune pairwise (mapping-privatization) scheme among a number of threads mapping scenarios that become available in the IR2 structure. Instrumentation on a subset of CHStone benchmark was carried out as a validity proof of our proposal, and the results confirmed that our framework kernel is robust.

关键词： Automatic parallelization parallel programming source-to-source compilation data dependency profiling parallelism assessment benchmarking

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Using source-to-source to Target RISC-V Custom Extensions: UVE Case-Study 24

Using Source-to-Source to Target RISC-V Custom Extensions: U...

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Rapido Workshop on Rapid Simulation and Performance Evaluation - Methods and Tools (Rapido) / HiPEAC Conference

作者： Henriques, Miguel Bispo, Joao Paulino, Nuno Univ Porto Porto Portugal Univ Porto INESC TEC Porto Portugal

ISBN: (纸本)9798400717918

Hardware specialization is seen as a promising venue for improving computing efficiency, with reconfigurable devices as excellent deployment platforms for application-specific architectures. One approach to hardware specialization is via the popular RISC-V, where Instruction Set Architecture (ISA) extensions for domains such as Edge Artifical Intelligence (AI) are already appearing. However, to use the custom instructions while maintaining a high (e.g., C/C++) abstraction level, the assembler and compiler must be modified. Alternatively, inline assembly can be manually introduced by a software developer with expert knowledge of the hardware modifications in the RISC-V core. In this paper, we consider a RISC-V core with a vectorization and streaming engine to support the Unlimited Vector Extension (UVE), and propose an approach to automatically transform annotated C loops into UVE compatible code, via automatic insertion of inline assembly. We rely on a source-to-source transformation tool, Clava, to perform sophisticated code analysis and transformations via scripts. We use pragmas to identify code sections amenable for vectorization and/or streaming, and use Clava to automatically insert inline UVE instructions, avoiding extensive modifications of existing compiler projects. We produce UVE binaries which are functionally correct, when compared to handwritten versions with inline assembly, and achieve equal and sometimes improved number of executed instructions, for a set of six benchmarks from the Polybench suite. These initial results are evidence towards that this kind of translation is feasible, and we consider that it is possible in future work to target more complex transformations or other ISA extensions, accelerating the adoption of hardware/software co-design flows for generic application cases.

关键词： Instruction Set Extension source-to-source compilation Hardware/Software co-design

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An OpenMP based Parallelization Compiler for C Applications 16

An OpenMP based Parallelization Compiler for C Applications

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16th IEEE ISPA / 17th IEEE IUCC / 8th IEEE BDCloud / 11th IEEE SocialCom / 8th IEEE SustainCom

作者： Arabnejad, Hamid Bispo, Joao Barbosa, Jorge G. Cardoso, Joao M. P. Univ Porto Fac Engn Porto Portugal Univ Porto Fac Engn LIACC Porto Portugal

ISBN: (纸本)9781728111414

Directive-drive programming models, such as OpenMP, are one solution for exploiting the potential of multi-core architectures, and enable developers to accelerate software applications by adding annotations on for-type loops and other code regions. However, manual parallelization of applications is known to be a non trivial and time consuming process, requiring parallel programming skills. Automatic parallelization approaches can reduce the burden on the application development side. This paper presents an OpenMP based automatic parallelization compiler, named AutoPar-Clava, for automatic identification and annotation of loops in C code. By using static analysis, parallelizable regions are detected, and a compilable OpenMP parallel code from the sequential version is produced. In order to reduce the accesses to shared memory by each thread, each variable is categorized into the proper OpenMP scoping. Also, AutoPar-Clava is able to support reduction on arrays, which is available since OpenMP 4.5. The effectiveness of AutoPar-Clava is evaluated by means of the Polyhedral Benchmark suite, and targeting a N-cores x86-based computing platform. The achieved results are very promising and compare favorably with closely related auto-parallelization compilers such as Intel C/C++ Compiler (i.e., icc), ROSE, TRACO, and Cetus.

关键词： Automatic Parallelization source-to-source compilation Parallel Programming Static Analysis

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AutoPar-Clava: An Automatic Parallelization source-to-source tool for C code applications 18

AutoPar-Clava: An Automatic Parallelization source-to-source...

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9th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures (PARMA) / 7th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (DITAM)

作者： Arabnejad, Hamid Bispo, Joao Barbosa, Jorge G. Cardoso, Joao M. P. Univ Porto Fac Engn FEUP Porto Portugal Univ Porto Fac Engn FEUP INESC TEC Porto Portugal Univ Porto Fac Engn FEUP LIACC Porto Portugal

ISBN: (纸本)9781450364447

Automatic parallelization of sequential code has become increasingly relevant in multicore programming. In particular, loop parallelization continues to be a promising optimization technique for scienti.c applications, and can provide considerable speedups for program execution. Furthermore, if we can verify that there are no true data dependencies between loop iterations, they can be easily parallelized. This paper describes Clava AutoPar, a library for the Clava weaver that performs automatic and symbolic parallelization of C code. The library is composed of two main parts, parallel loop detection and source-to-source code parallelization. The system is entirely automatic and attempts to statically detect parallel loops for a given input program, without any user intervention or profiling information. We obtained a geometric mean speedup of 1.5 for a set of programs from the C version of the NAS benchmark, and experimental results suggest that the performance obtained with Clava AutoPar is comparable or better than other similar research and commercial tools.

关键词： Automatic parallelization source-to-source compilation Parallel Programming OpenMP

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Extending OpenACC for Efficient Stencil Code Generation and Execution by Skeleton Frameworks 15

Extending OpenACC for Efficient Stencil Code Generation and ...

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15th International Conference on High Performance Computing & Simulation (HPCS)

作者： Pereira, Alyson D. Castro, Marcio Dantas, Mario A. R. Rocha, Rodrigo C. O. Goes, Luis F. W. Univ Fed Santa Catarina Florianopolis SC Brazil Univ Edinburgh Edinburgh Midlothian Scotland Pontificia Univ Catolica Minas Gerais Belo Horizonte MG Brazil

ISBN: (纸本)9781538632505

The OpenACC programming model simplifies the programming for accelerator devices such as GPUs. Its abstract accelerator model defines a least common denominator for accelerator devices, thus it cannot represent architectural specifics of these devices without losing portability. Therefore, this general-purpose approach delivers good performance on average, but it misses optimization opportunities for code generation and execution of specific classes of applications. In this paper, we propose OpenACC extensions to enable efficient code generation and execution of stencil applications by parallel skeleton frameworks such as PSkel. Our results show that our stencil extensions may improve the performance of OpenACC in up to 28% and 45% on GPU and CPU, respectively. Moreover, we show that the work-partitioning mechanism offered by the skeleton framework, which splits the computation across CPU and GPU, may improve even further the performance of the applications in up to 18%.

关键词： stencil skeleton frameworks source-to-source compilation CUDA OpenACC

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ImageCL: An Image Processing Language for Performance Portability on Heterogeneous Systems 14

ImageCL: An Image Processing Language for Performance Portab...

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International Workshop on Parallel Optimization using/for Multi and Many-Core High Performance Computing (POMCO) in conjunction with 14th International Conference on High Performance Computing and Simulation (HPCS)

作者： Falch, Thomas L. Elster, Anne C. Norwegian Univ Sci & Technol NTNU Trondheim Dept Comp & Info Sci Trondheim Norway Univ Texas Austin Inst Computat Engn & Sci Austin TX 78712 USA

ISBN: (纸本)9781509020881

Modern computer systems typically conbine multicore CPUs with accelerators like GPUs for inproved performance and energy efficiency. However, these systems suffer from poor performance portability - code tuned for one device must be retuned to achieve high performance on another. Image processing is increasing in importance, with applications ranging from seismology and medicine to Photoshop. Based on our experience with medical image processing, we propose ImageCL, a high-level domain-specific language and source-to-source compiler, targeting heterogeneous hardware. ImageCL resembles OpenCL, but abstracts away performance optimization details, allowing the programmer to focus on algorithm development, rather than performance tuning. The latter is left to our source-to-source compiler and auto-tuner. From high-level ImageCL kernels, our source-to-source compiler can generate multiple OpenCL implementations with different optimizations applied. We rely on auto-tuning rather than machine models or expert programmer knowledge to determine which optimizations to apply, making our tuning procedure highly robust. Furthermore, we can generate high performing implementations for different devices from a single source code, thereby improving performance portability. We evaluate our approach on three image processing benchmarks, on different GPU and CPU devices, and are able to outperform other state of the art solutions in several cases, achieving speedups of up to 4.57x.

关键词： performance portability source-to-source compilation auto-tuning heterogeneous computing image processing

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Enabling Dynamic Selection of Implementation Variants in Component-Based Parallel Programming for Heterogeneous Systems

Enabling Dynamic Selection of Implementation Variants in Com...

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29th International Conference on Parallel and Distributed Computing (Euro-Par)

作者： Memeti, Suejb Blekinge Inst Technol Dept Comp Sci DIDA Karlskrona Sweden

ISBN: (纸本)9783031506833;9783031506840

Heterogeneous systems, consisting of CPUs and GPUs, offer the capability to address the demands of compute- and data-intensive applications. However, programming such systems is challenging, requiring knowledge of various parallel programming frameworks. This paper introduces COMPAR, a component-based parallel programming framework that enables the exposure and selection of multiple implementation variants of components at runtime. The framework leverages compiler directive-based language extensions to annotate the source code and generate the necessary glue code for the StarPU runtime system. COMPAR provides a unified view of implementation variants and allows for intelligent selection based on runtime context. Our evaluation demonstrates the effectiveness of COMPAR through benchmark applications. The proposed approach simplifies heterogeneous parallel programming and promotes code reuse while achieving optimal performance.

关键词： component-based programming implementation variant selection heterogeneous parallel computing systems source-to-source compilation performance optimization

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HSTREAM: A directive-based language extension for heterogeneous stream computing 21

HSTREAM: A directive-based language extension for heterogene...

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21st IEEE International Conference on Computational Science and Engineering (CSE)

作者： Memeti, Suejb Pllana, Sabri Linnaeus Univ Dept Comp Sci Vaxjo Sweden

ISBN: (纸本)9781538676493

Big data streaming applications require utilization of heterogeneous parallel computing systems, which may comprise multiple multi-core CPUs and many-core accelerating devices such as NVIDIA GPUs and Intel Xeon Phis. Programming such systems require advanced knowledge of several hardware architectures and device-specific programming models, including OpenMP and CUDA. In this paper, we present HSTREAM, a compiler directive-based language extension to support programming stream computing applications for heterogeneous parallel computing systems. HSTREAM source-to-source compiler aims to increase the programming productivity by enabling programmers to annotate the parallel regions for heterogeneous execution and generate target specific code. The HSTREAM runtime automatically distributes the workload across CPUs and accelerating devices. We demonstrate the usefulness of HSTREAM language extension with various applications from the STREAM benchmark. Experimental evaluation results show that HSTREAM can keep the same programming simplicity as OpenMP, and the generated code can deliver performance beyond what CPUs-only and GPUs-only executions can deliver.

关键词： stream computing heterogeneous parallel computing systems source-to-source compilation

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ImageCL: Language and source-to-source compiler for performance portability, load balancing, and scalability prediction on heterogeneous systems

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CONCURRENCY AND COMPUTATION-PRACTICE & EXPERIENCE 2018年第9期30卷

作者： Falch, Thomas L. Elster, Anne C. Norwegian Univ Sci & Technol NTNU Dept Comp Sci Trondheim Norway

Applications written for heterogeneous CPU-GPU systems often suffer from poor performance portability. Finding good work partitions can also be challenging as different devices are suited for different applications. This article describes ImageCL, a high-level domain-specific language and source-to-source compiler, targeting single system as well as distributed heterogeneous hardware. Initially targeting image processing algorithms, our framework now also handles general stencil-based operations. It resembles OpenCL, but abstracts away performance optimization details which instead are handled by our source-to-source compiler. Machine learning-based auto-tuning is used to determine which optimizations to apply. For the distributed case, by measuring performance counters on a small input on one device, previously trained performance models are used to predict the throughput of the application on multiple different devices, making it possible to balance the load evenly. Models for the communication overhead are created in a similar fashion and used to predict the optimal number of nodes to use. ImageCL outperforms other state-of-the-art solutions on image processing benchmarks in several cases, achieving speedups of up to 4.57x. On both CPUs and GPUs we are only 3% and 2% slower than an oracle for load balancing and scalability prediction, respectively, using synthetic benchmarks.

关键词： load balancing machine learning source-to-source compilation performance portability scalability prediction

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