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9th IEEE International Conference on Networking, architecture, and Storage (NAS)

作者： Grawinkel, Matthias Best, Gregor Splietker, Malte Brinkmann, Andre Johannes Gutenberg Univ Mainz Mainz Germany Univ Paderborn Paderborn Germany

ISBN: (纸本)9781479940875

The need for huge storage systems rises with the ever growing creation of data. With growing capacities and shrinking prices, "write once read sometimes" workloads become more common. New data is constantly added, rarely updated or deleted, and every stored byte might be read at any time - a common pattern for digital archives or big data scenarios. We present the LoneStar stack, a disk based archival storage system building block that is optimized for high reliability and energy efficiency. It provides a POSIX file system interface that uses flash based storage for write-offloading and metadata and the disk-based LoneStar RAID for user data storage. The RAID attempts to spin down disks as soon and as long as possible. For reads, only a single disk is accessed, while writes require 3 additional parity disks to be spun up. The cache aggregates new files and a semantic data placement engine decides how they are persisted to the RAID. Asynchronous data movers then persist the data. The system provides an end-to-end data integrity, an elastic fault tolerance that can at least recover from all 3-disk failures, and provides multiple paths for data integrity checking and recovery. The system can use 70% of the raw disk capacity and is optimized for fast reads with a minimum number of powered on disk drives.

关键词： Ash Databases Diskdrives Nonvolatilememory Randomaccessmemory Reliability Spinning ArchivalStorage Disk Energy-efficient MAID disks Energy efficiency Spinning Ashes Database Murine Acquired Immunodeficiency Syndrome RAID stack architecture Spin cultivators Data Quality Cache memory Writing

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stack Multiple Shallow Autoencoders into a Strong One: A New Reconstruction-Based Method to Detect Anomaly 28th

Stack Multiple Shallow Autoencoders into a Strong One: A New...

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28th International Conference on Neural Information Processing

作者： Wang, Hanqi Hu, Xing Song, Liang Zhang, Guanhua Liu, Yang Liu, Jing Jiang, Linhua Fudan Univ Acad Engn & Technol Shanghai 200433 Peoples R China Univ Shanghai Sci & Technol Shanghai 200093 Peoples R China

ISBN: (纸本)9783030921842;9783030921859

Anomaly detection methods based on deep learning typically utilize reconstruction as a proxy task. These methods train a deep model to reconstruct the input from high-level features extracted from the samples. The underlying assumption of these methods is that a deep model trained on normal data would produce higher reconstruction error for abnormal input. But this underlying assumption is not always valid. Because the neural networks have a strong capacity to generalize, the deep model can also reconstruct the unseen abnormal input well sometimes, leading to a not prominent reconstruction error for abnormal input. Hence the decision-making process cannot distinguish the abnormal samples well. In this paper, we stack multiple shallow autoencoders (stackedAE) to enlarge the difference between reconstructions of normal and abnormal inputs. Our architecture feeds the output reconstruction of prior AE into the next one as input. For abnormal input, the iterative reconstruction process would gradually enlarge the reconstruction error. Our goal is to propose a general architecture that can be applied to different data types, e.g., video and image. For video data, we further introduce a weighted loss to emphasize the importance of the center frame and its near neighbors because it is unfair to treat all frames in a 3D convolution frame cuboid equally. To understand the effectiveness of our proposed method, we test on video datasets UCSD-Ped2, CUHK Avenue, and the image dataset MNIST. The results of the experiments demonstrate the effectiveness of our idea.

关键词： Image processing and computer vision Anomaly detection stack architecture Autoencoder Weighted reconstruction loss

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Synthetic pores with sticky π-clamps

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ORGANIC & BIOMOLECULAR CHEMISTRY 2007年第9期5卷 1369-1380页

作者： Tanaka, Hiroyuki Bollot, Guillaume Mareda, Jiri Litvinchuk, Svetlana Tran, Duy-Hien Sakai, Naomi Matile, Stefan Univ Geneva Dept Organ Chem CH-1211 Geneva Switzerland

In this report, we describe design, synthesis, evaluation and molecular dynamics simulations of synthetic multifunctional pores with pi-acidic naphthalenediimide clamps. Experimental evidence is provided for the formation of unstable but inert, heterogeneous and acid-insensitive dynamic tetrameric pores that are sensitive to base and ionic strength. Blockage experiments reveal that the introduction of aromatic electron donor - acceptor interactions provides access to the selective recognition of pi-basic intercalators within the pore. This breakthrough is important for the application of synthetic pores as multianalyte sensors.

关键词： ARTIFICIAL ION CHANNELS PEPTIDE-LIPID INTERACTIONS ROD BETA-BARRELS MULTIFUNCTIONAL PORES MOLECULAR RECOGNITION AQUEOUS-SOLUTION stack architecture ELECTRON-TRANSFER DNA MODEL

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Synthetic multifunctional nanoarchitecture in lipid bilayers: Ion channels, sensors, and photosystems

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BULLETIN OF THE CHEMICAL SOCIETY OF JAPAN 2007年第6期80卷 1044-1057页

作者： Bhosale, Rajesh Bhosale, Sheshanath Bollot, Guillaume Gorteau, Virginie Julliard, Marc D. Litvinchuk, Svetlana Mareda, Jiri Matile, Stefan Miyatake, Tomohiro Mora, Federico Perez-Velasco, Alejandro Sakai, Naomi Sisson, Adam L. Tanaka, Hiroyuki Tran, Duy-Hien Univ Geneva Dept Organ Chem CH-1211 Geneva Switzerland

The creation of functional materials such as ion channels, porous sensors, or smart photosystems depends critically on our ability to assemble sophisticated, error-free and self-repairing nanoarchitecture in a predictable manner. To address these challenging topics, we often used lipid bilayer membranes as compartmentalizing platform and have introduced rigid-rod molecules as privileged scaffolds that bypass all folding problems because they do not fold. This approach provides access to motifs such as rigid-rod barrels, helices, stacks, slides, and wires that can act as smart, stimuli-responsive photosystems, pores, ion channels, hosts, sensors, and catalysts. The selected examples focus on naphtha-lenediimides (NDIs), a compact, organizable, colorizable, and functionalizable n-semiconductor. This versatile module is used in rigid-rod molecules to mediate transmembrane anion transport by anion-pi interactions, as sticky pi-clamp within pore sensors to catch otherwise elusive analytes by aromatic electron donor-acceptor interactions, or in blue, transmembrane pi-stack architecture to collect and convert photonic energy. These specific examples with multifunctional NDI nanoarchitecture are of help to outline, on the one hand, possibilities to contribute to advanced functional materials such as multianalyte sensors or solar cells and, on the other hand, to keep on wondering about an enormous structural and functional space waiting to be explored.

关键词： Nanostructure solar cells stack architecture Lipid Bilayers Photosystems Functional Materials

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HOLISTIC COMPUTING

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MICROPROCESSORS AND MICROSYSTEMS 1995年第5期19卷 261-267页

作者： WISEMAN, SR FIELDRICHARDS, HS Defence Research Agency St. Andrews Road Malvern Worcestershire WR14 3PS UK.

An instruction set architecture is proposed which aims to reduce overall complexity in the high level language compilation process. The RISC approach moves complexity from the hardware into the compiler, while high level language instruction set computers move complexity from the compiler into the hardware. An alternative is proposed: the HOLISTIC approach. This has the aim of reducing overall complexity, rather than just moving it from one place to another, without compromising performance.

关键词： RISC stack architecture stack CACHE

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Ultrasonic transducers and arrays

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IEEE ENGINEERING IN MEDICINE AND BIOLOGY MAGAZINE 1996年第6期15卷 20-30页

作者： Shung, KK Zipparo, M Whitaker Center for Medical Ultrasonic Transducer Engineering Pennsylvania State University USA Pennsylvania State University University Park PA US

Ultrasonic imaging is one of the most important and still growing diagnostic tools in use today. To better understand transducer/array performance and some of the factors that prevent ultrasonic imagers from reaching higher resolution, this article reviews past achievements and current developments in the technology, including piezoelectric materials, transducer/array fabrication and design, and modeling. It is concluded that the array or transducer is a crucial part of an ultrasonic imaging system. Although much progress has been made in recent years to improve performance, it is still a limiting factor in preventing ultrasonic imaging systems from reaching their theoretical resolution. Investigations into novel piezoelectric materials, array stack architecture design, and modeling are being pursued. In the future, it is likely that multidimensional arrays will gradually replace linear arrays as the industry standard.

关键词： Modeling ultrasonic transducers Transducers arrays Technology Development stack architecture TOOL USE linear arrays diagnostic tool Ultrasonography Piezoelectric materials

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Vmgen - a generator of efficient virtual machine interpreters

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SOFTWARE-PRACTICE & EXPERIENCE 2002年第3期32卷 265-294页

作者： Ertl, MA Gregg, D Krall, A Paysan, B Vienna Tech Univ Inst Comp Sprachen A-1040 Vienna Austria Univ Dublin Trinity Coll Dept Comp Sci Dublin 2 Ireland

In a virtual machine interpreter, the code for each virtual machine instruction has similarities to code for other instructions. We present an interpreter generator that takes simple virtual machine instruction descriptions as input and generates C code for processing the instructions in several ways: execution, virtual machine code generation, disassembly, tracing, and profiling. The generator is designed to support efficient interpreters: it supports threaded code, caching the top-of-stack item in a register, combining simple instructions into superinstructions, and other optimizations. We have used the generator to create interpreters for Forth and Java. The resulting interpreters are faster than other interpreters for the same languages and they are typically 2-10 times slower than code produced by native-code compilers. We also present results for the effects of the individual optimizations supported by the generator. Copyright (C) 2002 John Wiley Sons, Ltd.

关键词： interpreter virtual machine generator stack architecture superinstruction byte code

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RegCPython: A Register-based Python Interpreter for Better Performance

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ACM TRANSACTIONS ON architecture AND CODE OPTIMIZATION 2022年第1期20卷 1-25页

作者： Zhang, Qiang Xu, Lei Xu, Baowen Nanjing Univ Dept Comp Sci & Technol State Key Lab Novel Software Technol 163 Xianlin Rd Nanjing 210023 Jiangsu Peoples R China

Interpreters are widely used in the implementation of many programming languages, such as Python, Perl, and Java. Even though various JIT compilers emerge in an endless stream, interpretation efficiency still plays a critical role in program performance. Does a stack-based interpreter or a register-based interpreter perform better? The pros and cons of the pair of architectures have long been discussed. The stack architecture is attractive for its concise model and compact bytecode, but our study finds that the register-based interpreter can also be implemented easily and that its bytecode size only grows by a small margin. Moreover, the latter turns out to be appreciably faster. Specifically, we implemented an open source Python interpreter named RegCPython based on CPython v3.10.1. The former is register based, while the latter is stack based. Without changes in syntax, Application Programming Interface, and Application Binary Interface, RegCPython is excellently compatible with CPython, as it does not break existing syntax or interfaces. It achieves a speedup of 1.287 on the most favorable benchmark and 0.977 even on the most unfavorable benchmark. For all Pythonintensive benchmarks, the average speedup reaches 1.120 on x86 and 1.130 on ARM. Our evaluation work, which also serves as an empirical study, provides a detailed performance survey of both interpreters on modern hardware. It points out that the register-based interpreters are more efficient mainly due to the elimination of machine instructions needed, while changes in branch mispredictions and cache misses have a limited impact on performance. Additionally, it confirms that the register-based implementation is also satisfactory in terms of memory footprint, compilation cost, and implementation complexity.

关键词： Python CPython interpreter register architecture stack architecture performance

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The case for virtual register machines

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SCIENCE OF COMPUTER PROGRAMMING 2005年第3期57卷 319-338页

作者： Gregg, D Beatty, A Casey, K Davis, B Nisbet, A Trinity Coll Dublin Dept Comp Sci Dublin 2 Ireland Manchester Metropolitan Univ Dept Comp & Math Manchester M1 5GD Lancs England

Virtual machines (VMs) are a popular target for language implementers. A long-running question in the design of virtual machines has been whether stack or register architectures can be implemented more efficiently with an interpreter. Many designers favour stack architectures since the location of operands is implicit in the stack pointer. In contrast, the operands of register machine instructions must be specified explicitly. In this paper, we present a working system for translating stack-based Java virtual machine (JVM) code to a simple register code. We describe the translation process, the complicated parts of the JVM which make translation more difficult, and the optimisations needed to eliminate copy instructions. Experimental results show that a register format reduced the number of executed instructions by 34.88%, while increasing the number of bytecode loads by an average of 44.81%. Overall, this corresponds to an increase of 2.32 loads for each dispatch removed. We believe that the high cost of dispatches makes register machines attractive even at the cost of increased loads. (c) 2005 Elsevier B.V. All rights reserved.

关键词： interpreter virtual machine register architecture stack architecture

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Virtual machine showdown: stack versus registers

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ACM TRANSACTIONS ON architecture AND CODE OPTIMIZATION 2007年第4期4卷 2-2页

作者： Shi, Yunhe Casey, Kevin Ertl, M. Anton Gregg, David Univ Dublin Trinity Coll Dept Comp Sci Dublin 2 Ireland Vienna Univ Technol Vienna Austria

Virtual machines (VMs) enable the distribution of programs in an architecture-neutral format, which can easily be interpreted or compiled. A long-running question in the design of VMs is whether a stack architecture or register architecture can be implemented more efficiently with an interpreter. We extend existing work on comparing virtual stack and virtual register architectures in three ways. First, our translation from stack to register code and optimization are much more sophisticated. The result is that we eliminate an average of more than 46% of executed VM instructions, with the bytecode size of the register machine being only 26% larger than that of the corresponding stack one. Second, we present a fully functional virtual-register implementation of the Java virtual machine (JVM), which supports Intel, AMD64, PowerPC and Alpha processors. This register VM supports inline-threaded, direct-threaded, token-threaded, and switch dispatch. Third, we present experimental results on a range of additional optimizations such as register allocation and elimination of redundant heap loads. On the AMD64 architecture the register machine using switch dispatch achieves an average speedup of 1.48 over the corresponding stack machine. Even using the more efficient inline-threaded dispatch, the register VM achieves a speedup of 1.15 over the equivalent stack-based VM.

关键词： performance language interpreter virtual machine register architecture stack architecture

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