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Miniaturization of Insertable Cardiac Monitor: ECG Signal Processing Based on stochastic computing

CIRCUITS SYSTEMS AND SIGNAL PROCESSING 2025年 1-32页

作者： Chen, Zhihao Ban, Tian Nanjing Univ Sci & Technol Sch Elect & Opt Engn Nanjing 210094 Jiangsu Peoples R China

The key requirements for medical implantable devices are low energy consumption and reliable computational precision. In this context, we design a novel filter for ECG signal denoising using the stochastic computing (SC) method. Compared to traditional binary methods, SC offers lower power consumption and reliable precision. Previous stochastic circuits use independent random number sources (RNS) to generate stochastic numbers (SN). In complex computing scenarios, multiple SNs require multiple groups of independent RNSs, leading to significant resource overhead, which negates the low power advantage of SC. Therefore, we propose a new shareable RNS that combines a nonlinear function with an LFSR. This RNS generates multiple SNs with low auto-correlation, which can be isolated from each other by simple de-correlation methods (such as inserting a delay unit). Additionally, improving precision substantially increases computation time, resulting in higher power consumption. Thus, we apply a low-delay stochastic multiplier to ECG signal processing to reduce computation time and power consumption of the implantable device.

关键词： stochastic computing LD sequence Nonlinear transformation Digital filter Walsh-spectrum FPGA

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An Area and Energy-Efficient Systolic Array Accelerator Architecture for Deep Neural Networks Using stochastic computing

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2025年

作者： Zhu, Jingwei Wu, Jingguo Yang, Zongru Jiang, Yu Chen, Yun Fudan Univ State Key Lab AS & Syst Shanghai 200433 Peoples R China

Deep neural networks (DNNs) are widely used to handle various intelligent tasks. With the increased model size, the DNNs' hardware accelerators are challenging the higher area overhead and energy consumption. stochastic computing (SC) has recently been considered for implementing DNNs and reducing hardware consumption. However, many current SC-based DNN accelerators fail to balance accuracy, performance, and resource overhead. In addition, their limited scalability and flexibility restrict their use in edge devices. In this article, we design an area and energy-efficient DNN accelerator architecture using SC. We propose an SC-binary hybrid processing unit with piecewise shift compensation without significant additional hardware overhead increment to improve the SC accuracy. To balance performance and resource overhead, we conduct a design space exploration (DSE) from an overall architectural perspective. An experimental platform with both software and hardware for SC-based DNNs is established. The software simulation results demonstrate that the best accuracy of the designed SC-DNN on the CIFAR-10 is 91.9%, which is 3.2% higher than that of the previous SC-DNN work. The VLSI implementation of the hardware is synthesized using the TSMC 28-nm CMOS process. Results show that compared to the binary computing counterpart, our design achieves 2.7 x area efficiency and 3.4 x energy efficiency. Compared to other SC-DNN accelerator designs, our design can provide 5.3 x area efficiency and 7.3 x energy efficiency.

关键词： stochastic processes Artificial neural networks Accuracy Correlation Hardware acceleration Energy efficiency Encoding Convolution Very large scale integration Logic gates Area efficient deep neural network (DNN) energy efficient stochastic computing

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Toward Universal Multiplexer Multiply-Accumulate Architecture in stochastic computing

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IEEE ACCESS 2025年 13卷 33874-33882页

作者： Lee, Yang Yang Halim, Zaini Abdul Ab Wahab, Mohd Nadhir Almohamad, Tarik Adnan Univ Sains Malaysia Sch Elect & Elect Engn Nibong Tebal 14300 Penang Malaysia Univ Sains Malaysia Sch Comp Sci Gelugor 11800 Penang Malaysia Karabuk Univ Fac Engn Dept Elect Elect Engn TR-78050 Karabuk Turkiye

stochastic computing (SC) has recently gained attraction due to its inherent error tolerance and extremely simple arithmetic hardware, making it particularly effective for accelerating modern applications such as neural networks on resource-constrained devices. Traditional SC architectures often adopt binary computing principles, relying on dedicated hardware, i.e. AND gates for multiplication and multiplexers (MUX) for addition. However, SC's mathematical foundation enables the fusion of complex operations into remarkably simple hardware. Several SC studies demonstrated the potential of MUX-based architectures to perform multiply-and-accumulate (MAC) operations, but existing designs face correlation complication, scaling problems, and limited application scope. This paper introduces an auxiliary logic block to address the complexity of MUX select inputs, significantly enhancing the scalability of MUX-based MAC operations. The proposed approach has been validated through SC image processing tasks, including grayscale conversion and Sobel edge detection, achieving up to 75% reduction in hardware resource utilization on field-programmable gate arrays (FPGAs) and up to 96% improvement in computational accuracy compared to traditional AND/XNOR-based SC multipliers.

关键词： Binary sequences Logic gates Hardware Arithmetic Correlation Logic Finite impulse response filters Field programmable gate arrays Adders Accuracy stochastic computing stochastic multiplier image processing field programmable gate array multiply-accumulate hardware

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PseudoSC: A Binary Approximation to stochastic computing within Latent Operation-Space for Ultra-Lightweight on-Edge DNNs 23

PseudoSC: A Binary Approximation to Stochastic Computing wit...

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Proceedings of the 60th Annual ACM/IEEE Design Automation Conference

作者： Jihe Wang Zhaoqing Wang Danghui Wang School of Computer Science Northwestern Polytechnical University Xi'an China Engineering Research Center of Embedded System Integration Ministry of Education Northwestern Polytechnical University Xi'an China National Engineering Laboratory for Integrated Aero-Space-Ground-Ocean Big Data Application Technology Northwestern Polytechnical University Xi'an China

ISBN: (纸本)9798350323481

Recently, stochastic computing (SC) is increasingly popular in constructing MAC for on-edge DNNs benefiting from its outstanding energy-efficiency, including its adequate precision and gatelevel operation. However, current SC-DNN systems always include a lot of costly SNGs/APCs for inevitably switches between binary and stochastic domains, which mortgages incongruous resources to pay the "bill" of the domain-switches and impedes highly-concurrent deployments. In this work, PseudoSC, a binary approximation to low-discrepancy SC, is proposed to totally remove the domain-switch for SNG/APC-free SC-DNNs. Its basic idea is to virtually re-arrange a couple of stochastic operands into a 2-D latent op-space, in which, original Monte Carlo sampling can be partitioned into three sub-ops, i.e., two fixed binary-ops and a fractal recursion. In theory, the recursion forms an isomorphic partition of the sampling repeated in smaller scales until the binary base-case achieved, as a result, a SC-op is well approximated only with binary-ops. Based on above theory, a multi-lane micro-architecture is designed to unroll the recursion within a few cycles and its advantages on hardware saving is verified under popular DNNs. The evaluation shows that the DNN-models with our schemes achieve 98.7% accuracy of the fixed-point implementations, which significantly outperform other SOTA methods. In addition, its reduced structure improves the power efficiency by 3.67 times on average.

关键词： stochastic computing

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Exploiting Omega Network and Inexact Accumulative Parallel Counter to Enhance Energy Efficiency in stochastic computing 25

Exploiting Omega Network and Inexact Accumulative Parallel C...

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Proceedings of the 40th ACM/SIGAPP Symposium on Applied computing

作者： Donghui Lee Yongtae Kim Kyungpook National University Daegu Republic of Korea

ISBN: (纸本)9798400706295

stochastic computing (SC) has garnered a great interest due to its energy efficiency and robustness against external noise, yet a long latency on stochastic computations and considerable overheads caused by conversions between binary numbers and stochastic numbers persist as notable challenges. This paper introduces a novel parallel random number generator (RNG) and accumulative parallel counters (APCs) to address both challenges. In particular, we propose a new parallel RNG design based on Omega network to bolster the randomness of generated numbers, thereby enhancing accuracy and reducing latency. Additionally, we introduce a novel APC design technique leveraging approximate 4-2 compressors to improve hardware efficiency while preserving the accuracy of SC computations. When implemented using a 65-nm CMOS technology, our proposed SC architecture outperforms other SC alternatives in terms of both hardware efficiency and computation accuracy. Specifically, our APC designs exhibit substantial enhancements of up to 30.1×, 26.6×, 5.9×, and 151× in area, power, delay, and energy, respectively, compared to traditional APCs. Also, we validate the efficacy of the proposed SC design through an image processing application, demonstrating superior processing quality alongside significantly enhanced hardware efficiency.

关键词： stochastic computing

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stochastic computing for Hardware Implementation of Binarized Neural Networks

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IEEE ACCESS 2019年 7卷 76394-76403页

作者： Hirtzlin, Tifenn Penkovsky, Bogdan Bocquet, Marc Klein, Jacques-Olivier Portal, Jean-Michel Querlioz, Damien Univ Paris Sud CNRS Ctr Nanosci & Nanotechnol F-91120 Palaiseau France Univ Aix Marseille & Toulon CNRS Inst Mat Microelect Nanosci Provence F-13451 Marseille France

Binarized neural networks, a recently discovered class of neural networks with minimal memory requirements and no reliance on multiplication, are a fantastic opportunity for the realization of compact and energy efficient inference hardware. However, such neural networks are generally not entirely binarized: their first layer remains with fixed point input. In this paper, we propose a stochastic computing version of binarized neural networks, where the input is also binarized. The simulations on the example of the Fashion-MNIST and CIFAR-10 datasets show that such networks can approach the performance of conventional binarized neural networks. We evidence that the training procedure should be adapted for use with stochastic computing. Finally, the ASIC implementation of our scheme is investigated, in a system that closely associates logic and memory, implemented by spin torque magnetoresistive random access memory. This analysis shows that the stochastic computing approach can allow considerable savings with regards to conventional binarized neural networks in terms of area (62% area reduction on the Fashion-MNIST task). It can also allow important savings in terms of energy consumption if we accept a reasonable reduction of accuracy: for example a factor 2.1 can be saved, with the cost of 1.4% in Fashion-MNIST test accuracy. These results highlight the high potential of binarized neural networks for hardware implementation, and that adapting them to hardware constraints can provide important benefits.

关键词： Binarized neural network stochastic computing embedded system MRAM in memory computing

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stochastic computing Improves the Timing-Error Tolerance and Latency of Turbo Decoders: Design Guidelines and Tradeoffs

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IEEE ACCESS 2016年 4卷 1008-1038页

作者： Perez-Andrade, Isaac Zhong, Shida Maunder, Robert G. Al-Hashimi, Bashir M. Hanzo, Lajos Univ Southampton Elect & Comp Sci Southampton SO17 1BJ Hants England

stochastic computing has been recently proposed for the hardware implementation of both low-density parity-check (LDPC) decoders and turbo decoders, which facilitate near-optimal error correction capabilities in wireless communication applications. Previous contributions have demonstrated that stochastic LDPC decoders offer an attractive tradeoff between their error correction capabilities, hardware performance, and timing-error tolerance. Motivated by this, we propose a pair of stochastic turbo decoder (S Ill) designs having significantly enhanced timing-error tolerance and significantly reduced processing latency. Moreover, we characterize the tradeoffs between chip area, energy efficiency, latency, throughput, and error correction capabilities of both the timing-error-tolerant S ID and of the reduced-latency S ID. We demonstrate that our proposed timing-error-tolerant S ID operated at 1.20 V, with a clock period of 2.2 ns and in the presence of a three-standard deviation power supply variation of 7%, exhibits an unimpaired performance, compared with the state-of-the-art S ID, operated at 1.20 V and 4 ns and with no power supply variations. This corresponds processing throughput improvement by a factor of 2.42 and energy consumption reduction by a factor of 4. Finally, we demonstrate that our proposed reduced-latency S ID has a processing latency that is an order of magnitude lower than that of the state-of-the-art STD. This is despite reducing the chip area by a factor of 4, increasing the processing throughput by a factor of 65, while consuming only 0.005 times the energy of the state-of-the-art S ID, when using binary phase-shift keying for communication over an additive white Gaussian noise channel having E-b/N-0 = 3 dB.

关键词： ASIC fault tolerance low-latency power supply variation stochastic computing timing errors turbo decoder

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stochastic computing Design and Implementation of a Sound Source Localization System

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IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS 2023年第1期13卷 295-311页

作者： Schober, Peter Estiri, Seyedeh Newsha Aygun, Sercan Jalilvand, Amir Hossein Najafi, M. Hassan TaheriNejad, Nima Tech Univ Wien Inst Comp Technol A-1040 Vienna Austria ITK Engn A-1110 Vienna Austria Univ Louisiana Sch Comp & Informat Lafayette LA 70503 USA Tech Univ Wien Inst Comp Technol ICT A-1040 Vienna Austria Heidelberg Univ Inst Comp Engn ZITI D-69120 Heidelberg Germany

stochastic computing (SC) is an alternative computing paradigm that processes data in the form of uniform bit-streams. SC is fault-tolerant and can compute on small, efficient circuits. However, SC is primarily used in scientific research, and its practical implementations for end-users are rare. Digital sound source localization (SSL) is a useful signal processing technique that locates speakers using multiple microphones. SC has not been integrated into SSL in practice or theory. In this work, for the first time to the best of our knowledge, we implement an SSL algorithm in the stochastic domain and develop a functional SC-based sound source localizer. The practical part of this work shows that the proposed stochastic circuit does not depend on conventional analog-to-digital conversion and can process data in the form of pulse-width-modulated (PWM) signals. The proposed SC design consumes up to 39% less area than the conventional binary design. It can also consume less power depending on the computational accuracy, for example, 6% less power consumption for 3-bit inputs. We propose a new cross-correlation (CC) design based on the state-of-the-art Sobol bit-streams for further area and power saving. The proposed design utilizes a MUX unit for bit-stream generation. It saves the area footprint up to 64% and the power consumption up to 82% compared to the counter-based SC design of CC, which relies on a comparator for bit-stream generation. The presented stochastic circuits, are not limited to SSL and are readily applicable to other practical applications such as radar ranging, wireless location, sonar direction finding, beamforming, and sensor calibration. The project's source code is made available for public access.

关键词： Audio processing cross-correlation digital design sound source localization stochastic computing

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stochastic computing in Beyond Von-Neumann Era: Processing Bit-Streams in Memristive Memory

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2022年第5期69卷 2423-2427页

作者： Riahi Alam, Mohsen Najafi, M. Hassan TaheriNejad, Nima Imani, Mohsen Gottumukkala, Raju Univ Louisiana Lafayette Sch Comp & Informat Lafayette LA 70503 USA Univ Louisiana Lafayette Dept Mech Engn Lafayette LA 70503 USA Tech Univ Wien Inst Comp Technol A-1040 Vienna Austria Univ Calif Irvine Dept Comp Sci Irvine CA 92697 USA

stochastic computing (SC) is an alternative computing paradigm that promises high robustness to noise and outstanding area- and power-efficiency compared to traditional binary. It also enables the design of fully parallel and scalable computations. Despite its advantage, SC suffers from long latency and high energy consumption compared to conventional binary computing, especially with current CMOS technology. The cost of conversion between binary and stochastic representation takes a significant cost with CMOS circuits. In-Memory Computation (IMC) is introduced to accelerate Big Data applications by removing the data movement between memory and processing units, and by providing massive parallelism. In this work, we explore the efforts in employing IMC for fast and energy-efficient SC system design. We specially focus on memristors as an emerging technology that promises efficient memory and computation beyond CMOS. We discuss the potentials and challenges for realizing efficient SC systems in memory.

关键词： Memristors stochastic processes Resistance Energy consumption Costs Random access memory Parallel processing stochastic computing in-memory computing resistive RAM emerging computing methods fault tolerant systems

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stochastic computing Based on Volatile GeSe Ovonic Threshold Switching Selectors

IEEE ELECTRON DEVICE LETTERS

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IEEE ELECTRON DEVICE LETTERS 2020年第10期41卷 1496-1499页

作者： Chai, Zheng Freitas, Pedro Zhang, Wei Dong Hatem, Firas Degraeve, Robin Clima, Sergiu Zhang, Jian Fu Marsland, John Fantini, Andrea Garbin, Daniele Goux, Ludovic Kar, Gouri Sankar Liverpool John Moores Univ Dept Elect & Elect Engn Liverpool L3 3AF Merseyside England IMEC B-3001 Leuven Belgium

stochastic computing (SC) is a special type of digital compute strategy where values are represented by the probability of 1 and 0 in stochastic bit streams, which leads to superior hardware simplicity and error-tolerance. In this letter, we propose and demonstrate SC with GeSe-based Ovonic Threshold Switching (OTS) selector devices by exploiting their probabilistic switching behavior. The stochastic bit streams generated by OTS are demonstrated with good computation accuracy in both multiplication operation and image processing circuit. Moreover, the bit distribution has been statistically studied and linked to the collective defect de/localization behavior in the chalcogenide material. Weibull distribution of the delay time supports the origin of such probabilistic switching, facilitates further optimization of the operation condition, and lays the foundation for device modelling and circuit design. Considering its other advantages such as simple structure, fast speed, and volatile nature, OTS is a promising material for implementing SC in a wide range of novel applications, such as image processors, neural networks, control systems and reliability analysis.

关键词： Switches Streaming media stochastic processes Probabilistic logic Image edge detection Weibull distribution Delays Selector GeSe stochastic computing memristor bit stream random number

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