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Chip optimization through STI-stress-aware placement perturbations and fill insertion

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2008年第7期27卷 1241-1252页

作者： Kahng, Andrew B. Sharma, Puneet Topaloglu, Rasit Onur Univ Calif San Diego Dept Comp Sci & Engn La Jolla CA 92093 USA Univ Calif San Diego Dept Elect & Comp Engn La Jolla CA 92093 USA Adv Micro Devices Inc Sunnyvale CA 94088 USA

Starting at the 65-nm node, stress engineering to improve the performance of transistors has been a major industry focus. An intrinsic stress source-shallow trench isolation (STI)-has not been fully utilized up to now for circuit performance improvement. In this paper, we present a new methodology that combines detailed placement and active-layer fill insertion to exploit STI stress for performance improvement. We conduct process simulation of a 65-nm production STI technology to generate mobility and delay impact models for STI stress. We then utilize these models to perform STI-stress-aware delay analysis of critical paths using Simulation Program with Integrated Circuit Emphasis (SPICE). We present our timing-driven optimization of STI stress in standard cell designs, using detailed placement perturbation and active-layer fill insertion to improve complementary metal-oxide-semiconductor performance. We assess the proposed analysis and optimization on small designs implemented with a 65-nm production cell library and a standard synthesis place-and-route flow. Our stress-aware timing analysis improves the clock frequency by 4.68% to 6.31% over traditional worst case analysis, and our optimization improves clock frequency by 2.44% to 5.26%. The frequency improvement through exploitation of STI stress comes at practically zero cost in terms of design area and wire length.

关键词： design for manufacturing (DFM) performance analysis and optimization shallow trench isolation (STI) stress modeling and optimization

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