In this paper, we present a novel off-chip network architecture, the Tile Serial Peripheral Interface (TSPI), designed for low-power, scalable edge AI accelerators. Our approach modifies the conventional SPI to suppor...
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In this paper, we present a novel off-chip network architecture, the Tile Serial Peripheral Interface (TSPI), designed for low-power, scalable edge AI accelerators. Our approach modifies the conventional SPI to support a modular network structure that facilitates the scalable connection of multiple accelerators. The TSPI network employs a subset mapping algorithm for efficient routing and integrates the message passing interface (MPI) protocol to ensure rapid data distribution and aggregation. This modular architecture significantly reduces power consumption and improves processing speed. Experimental results demonstrate that our proposed TSPI network achieves a 54.7% reduction in power consumption and an 82.3% decrease in switching power compared to traditional SPI networks, along with a 23% increase in processing speed when utilizing 16 nodes. These advancements make the TSPI network an effective solution for enhancing AI performance in edge computing environments.
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