This study addresses the problem of efficient faultsimulation and test generation in circuits using multi-output combinational logic cells. A symbolic fault simulation algorithm is proposed to exploit bit-level paral...
详细信息
This study addresses the problem of efficient faultsimulation and test generation in circuits using multi-output combinational logic cells. A symbolic fault simulation algorithm is proposed to exploit bit-level parallelism in order to represent the propagation of the output value of faulty cells throughout the circuit, thus accounting for different faulty behaviours in a single simulation step. A satisfiability (SAT)-based test generation procedure is also provided and it early discovers sets of undetectable behaviours. Results for a set of combinational benchmarks show the feasibility of the proposed approach.
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