With the transition from planar to three-dimensional transistor architectures, many new factors have entered the scene, highlighting the need for thorough investigation of ever-shrinking technology nodes, as well as t...
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With the transition from planar to three-dimensional transistor architectures, many new factors have entered the scene, highlighting the need for thorough investigation of ever-shrinking technology nodes, as well as the development of advanced methodologies capable of addressing the challenges of testing modern complex memory systems. This paper examines the challenges associated with Gate-All-Around emerging technology paradigm and proposes a conceptual framework aimed at comprehensively investigating the universe of realistic defects, accurately modeling the resulting faulty behavior, and ultimately developing effective test solutions.
Since the minimum feature size of dynamic RAM has been down-scaled, several studies have been carried out to determine ways to protect cell data from leakage current in many areas. In the field of testing, more approp...
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Since the minimum feature size of dynamic RAM has been down-scaled, several studies have been carried out to determine ways to protect cell data from leakage current in many areas. In the field of testing, more appropriate test algorithms are required to detect weak cells with leakage-current sources. In this paper, we propose an interleaving test algorithm that takes into account the equal bit-line stress regardless of the cell location. The proposed test algorithm allows screening of weak cells that cannot hold cell data due to the subthreshold leakage current. During the stress period, the algorithm can also detect other leakage currents. This paper presents the maximum stress differences according to the cell location, and determines the influence of the refresh operation on the maximum stress time. Therefore, this paper suggests a correlation between the refresh and read time to give maximum stress time.
A new stability test algorithm for two-dimensional (2-D) digital filters is proposed, which uses the inner term polynomials of the corresponding 2-D test polynomial to construct a test table in order to simplify the s...
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A new stability test algorithm for two-dimensional (2-D) digital filters is proposed, which uses the inner term polynomials of the corresponding 2-D test polynomial to construct a test table in order to simplify the stability test procedure. Different from other well-known table test algorithms, the new test algorithm can directly use the one-dimensional (1-D) Schur procedure to test the zeros' distribution of a 2-D complex polynomial in the unit bidisk.
FinFET transistors are playing an important role in modern technology that is rapidly growing. Embedded memories based on FinFET transistors lead to new defects that can require new embedded test and repair solution. ...
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ISBN:
(纸本)9781479926114
FinFET transistors are playing an important role in modern technology that is rapidly growing. Embedded memories based on FinFET transistors lead to new defects that can require new embedded test and repair solution. To investigate FinFET-specific faults the existing models and detection techniques are not enough due to a special structure of FinFET transistors. This paper presents a new strategy for investigation of FinFET-specific faults. In addition to fault modeling, a new method is proposed for test algorithm synthesis. The proposed methodology is validated on several real FinFET-based embedded memory technologies. Moreover, new faults are identified that are specific only to FinFETs.
Availability of defect test algorithm that recognizes exact and standardized defect information in order to fundamentally resolve generated defects in industrial sites by giving artificial intelligence to SAT(Scanning...
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ISBN:
(纸本)0878499385
Availability of defect test algorithm that recognizes exact and standardized defect information in order to fundamentally resolve generated defects in industrial sites by giving artificial intelligence to SAT(Scanning Acoustic Tomograph), which previously depended on operator's decision, to find various defect information in a semiconductor package, to decide defect pattern, to reduce personal errors and then to standardize the test process was verified. In order to apply the algorithm to the lately emerging Neural Network theory, various weights were used to derive results for performance advancement plans of the defect test algorithm that promises excellent field applicability.
This article discusses the problems of using compositions to increase the durability of friction units of power plants with the use of metal-cladding additives, as well as through the constant enrichment of engine oil...
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ISBN:
(纸本)9781665400756
This article discusses the problems of using compositions to increase the durability of friction units of power plants with the use of metal-cladding additives, as well as through the constant enrichment of engine oil with copper elements during operation. The dependence of the durability and efficiency of the use of agricultural machinery on the physicochemical and operational properties of lubricants has been determined. The mechanism of action of the modifier and the parameters of the protective layer are proposed. An algorithm for conducting tests has been formed, and key measurable quantities have been highlighted. An assessment of the effect of a metal-cladding additive on the main operational properties of an internal combustion engine has been made. The class assessment of the indicators of the modifier's work was carried out according to the point system. The influence of the modified engine oil on the quantitative indicator of combustion product deposits in the cylinder-piston group is considered. As a result of the study, the key features of the use of the modifier are highlighted.
The memory device used in high reliability field of aerospace needs fast fault diagnosis and location when function failure occurs, but simple function verification test can not even detect failure due to low fault co...
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ISBN:
(纸本)9781538682463
The memory device used in high reliability field of aerospace needs fast fault diagnosis and location when function failure occurs, but simple function verification test can not even detect failure due to low fault coverage. The combination test algorithm designed by using different memory test algorithms for the coverage difference of fault mode is analyzed by the results of multiple iterations, sometimes the fault points can be accurately positioned and the failure analysis is completed. Based on an example of SRAM failure analysis, a design method of combined test algorithm for fault diagnosis is presented.
This paper proposes a test algorithm that can detect and diagnose all the faults occurring in dual-port memories that can be accessed simultaneously through two ports. In this paper, we develop a new diagnosis algorit...
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This paper proposes a test algorithm that can detect and diagnose all the faults occurring in dual-port memories that can be accessed simultaneously through two ports. In this paper, we develop a new diagnosis algorithm that classifies faults in detail when they are detected while the test process is being developed. The algorithm is particularly efficient because it uses information that can be obtained by test results as well as results using an additional diagnosis pattern. The algorithm can also diagnose various fault models for dual-port memories.
As one of the most promising candidates for nonvolatile memory, phase change memory (PCM) technology has shown great performance advantages in market applications. However, the conventional test methods have not kept ...
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As one of the most promising candidates for nonvolatile memory, phase change memory (PCM) technology has shown great performance advantages in market applications. However, the conventional test methods have not kept pace with the development. In this article, focusing on specific PCM faults and others, an enhanced march test algorithm is proposed to achieve 100% fault coverage and diagnostic accuracy in bit-oriented PCM. The proposed algorithm is then converted for word-oriented PCM and equipped with capability to detect potential intraword impact. In addition, to reduce the dependence of memory test on the external devices, a novel storage scheme of fault information is devised. Through the modeling and simulation in C-language, this method is proven to improve the probability of finding the predefined fault-free regions in the tested memory. Finally, combining the enhanced test algorithm and the novel storage scheme, a built-in self-test (BIST) march test scheme is proposed, realizing the independent test of PCM without any external equipment. By comparison, the result of experiments, which are performed with C-language, proves that the proposed test scheme not only increases the fault coverage and diagnostic accuracy, but also reduces the additional area overhead.
This paper presents a unified global and local interconnect testing scheme for field programmable gate arrays. Adjacency graphs are used to model interconnect resources and their test requirements, and an efficient co...
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This paper presents a unified global and local interconnect testing scheme for field programmable gate arrays. Adjacency graphs are used to model interconnect resources and their test requirements, and an efficient computer algorithm for automatic derivation of test configurations is given. A device configuration generation tool was developed to reduce the test development cost.
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