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Fault Modeling and test algorithm Development Framework for Gate-All-Around SRAMs

IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY 2025年第1期25卷 37-44页

作者： Ghukasyan, Artur Amirkhanyan, Karen Tshagharyan, Grigor Harutyunyan, Gurgen Zorian, Yervant Synopsys Armenia CJSC Yerevan 0038 Armenia Synopsys Inc Sunnyvale CA 94085 USA

With the transition from planar to three-dimensional transistor architectures, many new factors have entered the scene, highlighting the need for thorough investigation of ever-shrinking technology nodes, as well as the development of advanced methodologies capable of addressing the challenges of testing modern complex memory systems. This paper examines the challenges associated with Gate-All-Around emerging technology paradigm and proposes a conceptual framework aimed at comprehensively investigating the universe of realistic defects, accurately modeling the resulting faulty behavior, and ultimately developing effective test solutions.

关键词： testing FinFETs Logic gates Memory management Scalability Nanowires Layout CNTFETs Materials reliability SPICE Fault modeling memory test gate-all-around inductive fault analysis test algorithm

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Development of a test algorithm and Evaluation of the Properties of a Metal-Cladding Additive

Development of a Test Algorithm and Evaluation of the Proper...

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Conference on Intelligent Technologies and Electronic Devices in Vehicle and Road Transport Complex (TIRVED)

作者： Gaidar, S. M. Ershov, V. S. Karelina, M. Yu Akulov, A. A. Russian State Agr Univ Moscow Timiryazev Agr Acad Moscow Russia Moscow Automobile & Rd Construct State Tech Univ Moscow Russia

ISBN: (纸本)9781665400756

This article discusses the problems of using compositions to increase the durability of friction units of power plants with the use of metal-cladding additives, as well as through the constant enrichment of engine oil with copper elements during operation. The dependence of the durability and efficiency of the use of agricultural machinery on the physicochemical and operational properties of lubricants has been determined. The mechanism of action of the modifier and the parameters of the protective layer are proposed. An algorithm for conducting tests has been formed, and key measurable quantities have been highlighted. An assessment of the effect of a metal-cladding additive on the main operational properties of an internal combustion engine has been made. The class assessment of the indicators of the modifier's work was carried out according to the point system. The influence of the modified engine oil on the quantitative indicator of combustion product deposits in the cylinder-piston group is considered. As a result of the study, the key features of the use of the modifier are highlighted.

关键词： additive reliability internal combustion engine test algorithm improved performance

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Design of combinatorial test algorithm for memory fault diagnosis 8

Design of combinatorial test algorithm for memory fault diag...

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8th International Conference on Instrumentation and Measurement, Computer, Communication and Control (IMCCC)

作者： Zhang Dayu Wang Yue Wang He Zhang Song Jiang Chengzhi China Acad Space Technol Beijing Peoples R China

ISBN: (纸本)9781538682463

The memory device used in high reliability field of aerospace needs fast fault diagnosis and location when function failure occurs, but simple function verification test can not even detect failure due to low fault coverage. The combination test algorithm designed by using different memory test algorithms for the coverage difference of fault mode is analyzed by the results of multiple iterations, sometimes the fault points can be accurately positioned and the failure analysis is completed. Based on an example of SRAM failure analysis, a design method of combined test algorithm for fault diagnosis is presented.

关键词： test algorithm fault diagnosis memory device high reliability field fault mode

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BIST-Based Fault Diagnosis for PCM With Enhanced test Scheme and Fault-Free Region Finding algorithm

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2020年第7期28卷 1652-1664页

作者： Xie, Chenchen Li, Xi Lei, Yu Chen, Houpeng Wang, Qian Guo, Jiashu Miao, Jie Lv, Yi Song, Zhitang Chinese Acad Sci Shanghai Inst Microsyst & Informat Technol State Key Lab Funct Mat Informat Shanghai 200050 Peoples R China Univ Chinese Acad Sci Beijing 100049 Peoples R China Shanghai Technol Dev & Entrepreneurship Platform Shanghai 20090 Peoples R China AI SoC Shanghai 20090 Peoples R China

As one of the most promising candidates for nonvolatile memory, phase change memory (PCM) technology has shown great performance advantages in market applications. However, the conventional test methods have not kept pace with the development. In this article, focusing on specific PCM faults and others, an enhanced march test algorithm is proposed to achieve 100% fault coverage and diagnostic accuracy in bit-oriented PCM. The proposed algorithm is then converted for word-oriented PCM and equipped with capability to detect potential intraword impact. In addition, to reduce the dependence of memory test on the external devices, a novel storage scheme of fault information is devised. Through the modeling and simulation in C-language, this method is proven to improve the probability of finding the predefined fault-free regions in the tested memory. Finally, combining the enhanced test algorithm and the novel storage scheme, a built-in self-test (BIST) march test scheme is proposed, realizing the independent test of PCM without any external equipment. By comparison, the result of experiments, which are performed with C-language, proves that the proposed test scheme not only increases the fault coverage and diagnostic accuracy, but also reduces the additional area overhead.

关键词： Phase change materials Built-in self-test Circuit faults Very large scale integration Micromechanical devices Information technology Resistance Built-in self-test (BIST) fault-free region (FFR) phase change memory (PCM) test algorithm test scheme

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Interleaving test algorithm for Subthreshold Leakage-Current Defects in DRAM Considering the Equal Bit Line Stress

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2014年第4期22卷 803-812页

作者： Shin, Hyoyoung Park, Youngkyu Lee, Gihwa Park, Jungsik Kang, Sungho Yonsei Univ Dept Elect & Elect Engn Seoul 120749 South Korea Hynix Semicond Inc Mfg Div Gyounggi Do 467701 South Korea

Since the minimum feature size of dynamic RAM has been down-scaled, several studies have been carried out to determine ways to protect cell data from leakage current in many areas. In the field of testing, more appropriate test algorithms are required to detect weak cells with leakage-current sources. In this paper, we propose an interleaving test algorithm that takes into account the equal bit-line stress regardless of the cell location. The proposed test algorithm allows screening of weak cells that cannot hold cell data due to the subthreshold leakage current. During the stress period, the algorithm can also detect other leakage currents. This paper presents the maximum stress differences according to the cell location, and determines the influence of the refresh operation on the maximum stress time. Therefore, this paper suggests a correlation between the refresh and read time to give maximum stress time.

关键词： Bit-line stress time maximum stress time subthreshold leakage-current defect test algorithm

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Fault Modeling and test algorithm Creation Strategy for FinFET-Based Memories

Fault Modeling and Test Algorithm Creation Strategy for FinF...

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IEEE 32nd VLSI test SYMPOSIUM (VTS)

作者： Harutyunyan, G. Tshagharyan, G. Vardanian, V. Zorian, Y. Synopsys|c|

ISBN: (纸本)9781479926114

FinFET transistors are playing an important role in modern technology that is rapidly growing. Embedded memories based on FinFET transistors lead to new defects that can require new embedded test and repair solution. To investigate FinFET-specific faults the existing models and detection techniques are not enough due to a special structure of FinFET transistors. This paper presents a new strategy for investigation of FinFET-specific faults. In addition to fault modeling, a new method is proposed for test algorithm synthesis. The proposed methodology is validated on several real FinFET-based embedded memory technologies. Moreover, new faults are identified that are specific only to FinFETs.

关键词： FinFET defect fault model test algorithm embedded memory

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An SRAM test Quality Improvement Method For Automotive chips 5

An SRAM Test Quality Improvement Method For Automotive chips

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5th IEEE International test Conference in Asia (ITC-Asia)

作者： Xu, Tuanhui Huang, Junlin Bu, Mingen Jiang, Zhe Hisilicon Technol Co LTD Shenzhen Peoples R China

ISBN: (纸本)9781665413343

Automotive chips have high requirements on chip test quality. The degree of defects covered by the SRAM test algorithm directly determines the test quality of SRAM. With the evolution of IC manufacturing technology, the defect modeling of SRAM becomes more and more complicated. How to establish a complete test algorithm has become a challenge in the industry. Currently, the industry develops a new test algorithm by establishing defect models on the advanced process nodes. However, the defect model is different from the defect in the actual process. The mass production test shows that many chips are in the critical defect state and cannot be detected. In this paper, we propose an improved memory defect analysis method, and develop a novel defect and test scheme. The mass production test results show that this test scheme can detect the critical defect chips effectively.

关键词： MBIST test algorithm dynamic faults defect simulation automotive

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Fault Modeling and testing of Memristor-Based Spiking Neural Networks

Fault Modeling and Testing of Memristor-Based Spiking Neural...

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IEEE International test Conference (ITC)

作者： Hou, Kuan-Wei Cheng, Hsueh-Hung Tung, Chi Wu, Cheng-Wen Lu, Juin-Ming Natl Tsing Hua Univ Dept Elect Engn Hsinchu Taiwan Ind Technol Res Inst Hsinchu Taiwan

ISBN: (数字)9781665462709

ISBN: (纸本)9781665462709

The resistive random-access memory (RRAM), whose core is composed of memristor cell arrays, has recently been proposed for implementing the deep neural network (DNN) and spiking neural network (SNN), which potentially can improve the performance and energy efficiency of AI computing. In this paper, we address highquality memristor-based SNNs. We propose two functional fault models for them, i.e., the Slow Integration Fault (SIF) and Fast Integration Fault (FIF), and show the circuit-level fault simulation results, taking process variation into account. The detailed simulation and analysis results show that the SIF and FIF are feasible functional fault models for memristor-based SNNs, as the interconnect open and short defects, as well as the memristor and transistor faults, can all be covered by the proposed SIF and FIF. We have also developed a test algorithm for the SNNs, i.e., the SNN-test algorithm. Experimental results show that the SNN-test covers 100% of the open and short defects and the proposed functional fault models.

关键词： Memnistor Spiking Neural Network In-Memory Computing Fault Model Fault Simulator test algorithm

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A VDD Correction Method for Static Stability test of SRAM Bit Cell

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IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY 2020年第3期20卷 530-540页

作者： Liu, Yuyan Shi, Zheng Pan, Weiwei Lan, Fan Zhejiang Univ Inst VLSI Design Hangzhou 310027 Peoples R China Semitronix Corp Hangzhou 310012 Peoples R China

SRAM stability is a major concern in nanometer CMOS technologies. As the most important metrics of SRAM static stability, the static characteristics of SRAM are derived by static characteristic curves (read butterfly curve, standby butterfly curve, read N curve, write N curve and WNM curve). This paper deduces the read butterfly curve transfer function as an example to show the effect of supply voltage deviation. In order to increase the quantity of SRAM DUTs (Device under tests) and test accuracy, we propose a test method with VDD correction which eliminates the effect of supply voltage deviation. First, an addressable test structure is applied, where the transmission gates are used to force and sense the node voltages, and then correct the voltages. Second, a test algorithm with fast convergence combining the bisection method and PID (Proportion Integral Differential) algorithm is proposed to correct the voltages. SPICE simulations show that the proposed method reduces the error from approximately 10% (commonly used methods) to less than 2%. It is further implemented in a standard 55nm CMOS process, and the static characteristic curves of 1k-bits SRAM DUTs are measured within the accuracy range of 1 mV, which fit well with the simulation results, indicating the method can accurately measure 1k-bits DUTs.

关键词： Random access memory Stability analysis Voltage measurement Transistors Logic gates Current measurement testing Addressable test structure force and sense VDD correction test algorithm bisection method PID algorithm SNM static characteristics

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Method of Alloying Engine Oil with Complex Copper Compounds

Method of Alloying Engine Oil with Complex Copper Compounds

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Conference on Intelligent Technologies and Electronic Devices in Vehicle and Road Transport Complex (TIRVED)

作者： Ershov, V. S. Gaidar, S. M. Karelina, M. Yu Akulov, A. A. Moscow Automobile & Rd Construct State Tech Univ Moscow Russia Russian State Agr Univ Moscow Timiryazev Agr Acad Moscow Russia

ISBN: (纸本)9781665400756

This paper presents a method of alloying engine oil with complex copper compounds, which can significantly reduce wear on rubbing surfaces and increase the reliability of the internal combustion engine by transferring copper from the alloy to the surface. A device for alloying engine oil with copper-containing elements has been developed. The process of copper cladding of surfaces of movable joints of machines and mechanisms is described. The dependence between the number of copper particles in the lubricating medium, the size of the copper element area and the ligand concentration in the lubricant is revealed. The study of steel samples for corrosion resistance in different lubricating environments has been carried out. The experiment to determine the dissolution rate of copper depending on the amount of ligand in the base oil has been conducted, as well as to determine the optimal amount of copper. The article analyzes the economic effect of using a metal-plating additive (MPA) in the operation of a vehicle.

关键词： additive reliability internal combustion engine test algorithm performance improvement

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