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检索条件"主题词=test algorithm"
37 条 记 录,以下是11-20 订阅
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A new method to evaluate interlacing yarns
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TEXTILE RESEARCH JOURNAL 2020年 第7-8期90卷 838-846页
作者: Wang, Meng Zhan, Yinlan Yao, Leon Ningbo Shenzhou Knitting Co Ltd 636 Fuchunjiang Rd Ningbo 315000 Zhejiang Peoples R China
The theory of purification is proposed in this article. Based on the framework of this theory, several models can be built to give a synthetic quality evaluation of interlacing yarns. In this paper, three models are g... 详细信息
来源: 评论
testing Neighbouring Cell Leakage and Transition Induced Faults in DRAMs
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IEEE TRANSACTIONS ON COMPUTERS 2016年 第7期65卷 2339-2345页
作者: Sfikas, Yiorgos Tsiatouhas, Yiorgos Univ Ioannina Dept Comp Sci & Engn POB 1186 GR-45110 Ioannina Greece
Due to their high density, modern DRAMs are very susceptible to the interactions between adjacent cells, which in turn increases the difficulty and complexity of memory testing. In this work, we studied the interactio... 详细信息
来源: 评论
Fault Modeling and testing of Resistive Nonvolatile-8T SRAMs  34
Fault Modeling and Testing of Resistive Nonvolatile-8T SRAMs
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IEEE 34th VLSI test Symposium (VTS)
作者: Li, Yu-Ting Chen, Yong-Xiao Li, Jin-Fu Natl Cent Univ Dept Elect Engn Taoyuan 320 Taiwan
In modern system-on-chips (SOCs), static power consumption represents a significant portion of the chip power. Since static random access memory (SRAM) typically occupies more than one half of the chip area, static po... 详细信息
来源: 评论
test and Repair Methodology for FinFET-Based Memories
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IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY 2015年 第1期15卷 3-9页
作者: Harutyunyan, Gurgen Tshagharyan, Grigor Zorian, Yervant Synopsys Inc Yerevan 0026 Armenia Synopsys Inc Mountain View CA 94043 USA
FinFET transistors are commonly acknowledged as the most promising technology able to play a crucial role to route the development of rapidly growing modern silicon industry. Embedded memories, based on FinFET transis... 详细信息
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Impact of Parameter Variations on FinFET Faults  33
Impact of Parameter Variations on FinFET Faults
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2015 IEEE 33rd VLSI test SYMPOSIUM (VTS)
作者: Harutyunyan, G. Tshagharyan, G. Zorian, Y. Synopsys Hyderabad Telangana India
The technology shrinking strategy below 20nm feature sizes adopted by the giants of the nowadays semiconductor industry has boosted the research on FinFET which is considered as an alternative to the conventional plan... 详细信息
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On Resistive Open Defect Detection in DRAMs: The Charge Accumulation Effect  20
On Resistive Open Defect Detection in DRAMs: The Charge Accu...
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20th IEEE European test Symposium (ETS)
作者: Sfikas, Yiorgos Tsiatouhas, Yiorgos Taouil, Mottaqiallah Hamdioui, Said Univ Ioannina Dept Comp Sci & Engn GR-45110 Ioannina Greece Delft Univ Technol Comp Engn Lab NL-2628 CD Delft Netherlands
The test complexity of high density DRAMs increases with technology evolution, due to a larger impact of process variation and weak defects. In particular, resistive open defects turn to be a major concern in DRAMs. O... 详细信息
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Automatic Control System for Memory Chips Performance in a Radiation Experiment
Automatic Control System for Memory Chips Performance in a R...
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International Siberian Conference on Control and Communications (SIBCON)
作者: Boruzdina, A. B. Orlov, A. A. Ulanova, A. V. Grigor'ev, N. G. Nikiforov, A. Y. Natl Res Nucl Univ MEPhI Moscow Engn Phys Inst Moscow Russia
The paper analyzes the effectiveness of test algorithms of different duration during the functional control of static random access memory (SRAM) during the exposure to total ionizin dose (TID). The results of experim... 详细信息
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Fault Modeling and testing of Resistive Nonvolatile-8T SRAMs
Fault Modeling and Testing of Resistive Nonvolatile-8T SRAMs
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IEEE VLSI test Symposium
作者: Yu-Ting Li Yong-Xiao Chen Jin-Fu Li Department of Electrical Engineering National Central University
In modern system-on-chips (SOCs), static power consumption represents a significant portion of the chip power. Since static random access memory (SRAM) typically occupies more than one half of the chip area, static po... 详细信息
来源: 评论
test Solution for Data Retention Faults in Low-Power SRAMs
Test Solution for Data Retention Faults in Low-Power SRAMs
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Design, Automation and test in Europe Conference and Exhibition (DATE)
作者: Zordan, L. B. Bosio, A. Dilillo, L. Girard, P. Todri, A. Virazel, A. Badereddine, N. Univ Montpellier 2 CNRS LIRMM 161 Rue Ada F-34095 Montpellier 5 France Intel Mobile Commun F-06560 Sophia Antipolis France
Low-power SRAMs embed mechanisms for reducing static power consumption. When the SRAM is not accessed during a long period, it switches into an intermediate low-power mode. In this mode, a voltage regulator is used to... 详细信息
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Application of Defect Injection Flow for Fault Validation in Memories
Application of Defect Injection Flow for Fault Validation in...
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IEEE East-West Design and test Symposium (EWDTS)
作者: Amirkhanyan, K. Davtyan, A. Harutyunyan, G. Melkumyan, T. Shoukourian, S. Vardanian, V. Zorian, Y. Synopsys Mountain View CA 94043 USA
In the paper, an advanced flow for defect injection in the memories and its application for fault validation are presented. Specifically, the results of injecting address decoder and process variation defects are illu... 详细信息
来源: 评论