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A VDD Correction Method for Static Stability test of SRAM Bit Cell

IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY 2020年第3期20卷 530-540页

作者： Liu, Yuyan Shi, Zheng Pan, Weiwei Lan, Fan Zhejiang Univ Inst VLSI Design Hangzhou 310027 Peoples R China Semitronix Corp Hangzhou 310012 Peoples R China

SRAM stability is a major concern in nanometer CMOS technologies. As the most important metrics of SRAM static stability, the static characteristics of SRAM are derived by static characteristic curves (read butterfly curve, standby butterfly curve, read N curve, write N curve and WNM curve). This paper deduces the read butterfly curve transfer function as an example to show the effect of supply voltage deviation. In order to increase the quantity of SRAM DUTs (Device under tests) and test accuracy, we propose a test method with VDD correction which eliminates the effect of supply voltage deviation. First, an addressable test structure is applied, where the transmission gates are used to force and sense the node voltages, and then correct the voltages. Second, a test algorithm with fast convergence combining the bisection method and PID (Proportion Integral Differential) algorithm is proposed to correct the voltages. SPICE simulations show that the proposed method reduces the error from approximately 10% (commonly used methods) to less than 2%. It is further implemented in a standard 55nm CMOS process, and the static characteristic curves of 1k-bits SRAM DUTs are measured within the accuracy range of 1 mV, which fit well with the simulation results, indicating the method can accurately measure 1k-bits DUTs.

关键词： Random access memory Stability analysis Voltage measurement Transistors Logic gates Current measurement testing Addressable test structure force and sense VDD correction test algorithm bisection method PID algorithm SNM static characteristics

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test-GENERATION AND FAULT-DETECTION FOR VLSI PPL CIRCUITS

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INTEGRATION-THE VLSI JOURNAL 1989年第3期7卷 303-324页

作者： AMIN, AAM SMITH, KF Department of Computer Science The University of Utah Salt Lake City UT 84112 U.S.A.

This work describes a test generation package developed to utilize the special features of PPL arrays (a structured logic design methodology developed by the VLSI group at the University of Utah) to generate high fault coverage test vectors at a reduced computational cost. The test strategy assumes that one of the scan design techniques is used. A fault oriented test generation algorithm combined with a heuristic test generation algorithm are the essential ingredients of this package. The heuristic algorithm generates an initial set of test vectors which is verified against a predefined list of possible faults. A fault oriented algorithm is then used to generate test vectors that can detect faults not detected by this set. The fault oriented algorithm uses a modified D -algorithm which includes look ahead features and a new seven valued logic to improve the average speed of the test generation process. Fault coverages in the 90% range were obtained using the test vectors generated by this package. test vectors generated by both algorithms can optionally be stitched into sequences in a way that does not compromise their fault coverage. This reduces the overhead in actual test application time by cutting down the number of the serial scan in/out operations.

关键词： Fault test vector scan path D -algorithm test algorithm fault coverage fault collapsing fault provoking path sensitization

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test and Repair Methodology for FinFET-Based Memories

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IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY 2015年第1期15卷 3-9页

作者： Harutyunyan, Gurgen Tshagharyan, Grigor Zorian, Yervant Synopsys Inc Yerevan 0026 Armenia Synopsys Inc Mountain View CA 94043 USA

FinFET transistors are commonly acknowledged as the most promising technology able to play a crucial role to route the development of rapidly growing modern silicon industry. Embedded memories, based on FinFET transistors, lead to new defect types that can require new embedded test and repair solutions. To investigate FinFET-specific faults, the existing fault models and detection techniques are not enough because of the spatial structure of FinFET transistors. This paper presents the results of the comprehensive study carried out for FinFET-based memories based on a new fault modeling and test algorithm creation strategy. The proposed solution is validated on several real FinFET-based embedded memory technologies.

关键词： FinFET defect fault modeling test algorithm embedded memory

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Implementation of a BIST scheme for ADC test 5

Implementation of a BIST scheme for ADC test

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5th International Conference on ASIC

作者： Wu, GL Rao, J Ren, AL Ling, M Southeast Univ Natl ASIC Syst Engn Ctr Nanjing 210096 Peoples R China

ISBN: (纸本)078037889X

(I)n this paper, we presented algorithms for testing gain error. offset error. differential nonlinearity (DNL) and integral nonlinearity (INL) of analog-to-digital converters (ADC). and proposed an easily integrated built-in self-test (BIST) scheme on chip, which has been designed using TSMC 0.25mum technology. The experimental results show that the proposed BIST scheme has low area overhead, low test cost and high test accuracy.

关键词： test algorithm BIST area ADC

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An SRAM test Quality Improvement Method For Automotive chips 5

An SRAM Test Quality Improvement Method For Automotive chips

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5th IEEE International test Conference in Asia (ITC-Asia)

作者： Xu, Tuanhui Huang, Junlin Bu, Mingen Jiang, Zhe Hisilicon Technol Co LTD Shenzhen Peoples R China

ISBN: (纸本)9781665413343

Automotive chips have high requirements on chip test quality. The degree of defects covered by the SRAM test algorithm directly determines the test quality of SRAM. With the evolution of IC manufacturing technology, the defect modeling of SRAM becomes more and more complicated. How to establish a complete test algorithm has become a challenge in the industry. Currently, the industry develops a new test algorithm by establishing defect models on the advanced process nodes. However, the defect model is different from the defect in the actual process. The mass production test shows that many chips are in the critical defect state and cannot be detected. In this paper, we propose an improved memory defect analysis method, and develop a novel defect and test scheme. The mass production test results show that this test scheme can detect the critical defect chips effectively.

关键词： MBIST test algorithm dynamic faults defect simulation automotive

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test Solution for Data Retention Faults in Low-Power SRAMs

Test Solution for Data Retention Faults in Low-Power SRAMs

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Design, Automation and test in Europe Conference and Exhibition (DATE)

作者： Zordan, L. B. Bosio, A. Dilillo, L. Girard, P. Todri, A. Virazel, A. Badereddine, N. Univ Montpellier 2 CNRS LIRMM 161 Rue Ada F-34095 Montpellier 5 France Intel Mobile Commun F-06560 Sophia Antipolis France

ISBN: (纸本)9783981537000

Low-power SRAMs embed mechanisms for reducing static power consumption. When the SRAM is not accessed during a long period, it switches into an intermediate low-power mode. In this mode, a voltage regulator is used to reduce the voltage supplied to the core-cells as low as possible without data loss. Thus, faulty-free behavior of the voltage regulator is crucial for ensuring data retention in core-cells when the SRAM is in low-power mode. This paper investigates the root cause of data retention faults due to voltage regulator malfunctions. This analysis is done under realistic conditions (i.e., industrial core-cells affected by process variations). Based on this analysis, we propose an efficient test flow for detecting data retention faults in low-power SRAMs.

关键词： SRAM low-power design test algorithm memory test

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Modeling and test for Parasitic Resistance and Capacitance Defects in PCM

Modeling and Test for Parasitic Resistance and Capacitance D...

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12th Annual Non-Volatile Memory Technology Symposium

作者： Pan, Xiujuan Cui, Xiaole Zha, Jin Lin, Xinnan Lee, Chung Len Peking Univ Shenzhen Grad Sch Key Lab Integrated Microsyst Shenzhen Peoples R China

ISBN: (纸本)9781467328487

Parasitic capacitance and resistance have much influence on the performance of the phase change memory (PCM). Based on SPICE circuit simulations, this paper investigates possible faults caused by the parasitic capacitance and resistance defects in stand-alone PCM cells. A realistic set of fault models are proposed and a test algorithm is proposed to test the faults.

关键词： PCM capacitance and resistance defects SPICE model fault model test algorithm

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试探算法与SSOR预处理共轭梯度算法的拟最佳因子

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高等学校计算数学学报 2007年第2期29卷 176-185页

作者：彭小飞向淑晃黎稳华南师范大学数学科学学院中南大学数学科学与计算技术学院

1引言在求解系数矩阵为对称正定的大型线性代数方程组Au=b (1．1)的迭代法方面,七十年代以来发展了各种预处理共轭梯度法．由于SSOR分裂中具有对称因子,可用于加速共轭梯度法,称为SSOR预处理共轭梯度法(简记为;SSORPCG．同时,由于当松... 详细信息

1引言在求解系数矩阵为对称正定的大型线性代数方程组Au=b (1．1)的迭代法方面,七十年代以来发展了各种预处理共轭梯度法．由于SSOR分裂中具有对称因子,可用于加速共轭梯度法,称为SSOR预处理共轭梯度法(简记为;SSORPCG．同时,由于当松弛因子ω∈(0,2)时,SSOR迭代法收敛,从而进一步发展了m步SSOR预处理共轭梯度法(简记为:m-step SSORPCG．胡家赣证明,经过最优的SSOR预条件,预优

关键词： test algorithm optimum relaxation factor quasi-optimum relaxation factor ssorpcg.

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testing content addressable memories with physical fault models

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Journal of Semiconductors 2009年第8期30卷 109-115页

作者：马麟杨旭钟石强陈云霁 Institute of Computing Technology Chinese Academy of Sciences Graduate University of the Chinese Academy of Sciences

Content addressable memory （CAM） is widely used and its tests mostly use functional fault models. However, functional fault models cannot describe some physical faults exactly. This paper introduces physical fault models for write-only CAM. Two test algorithms which can cover 100% targeted physical faults are also proposed. The algorithm for a CAM module with N-bit match output signal needs only 2N＋2L＋4 comparison operations and 5N writing operations, where N is the number of words and L is the word length. The algorithm for a HIT-signal-only CAM module uses 2N＋2L＋5 comparison operations and 8N writing operations. Compared to previous work, the proposed algorithms can test more physical faults with a few more operations. An experiment on a test chip shows the effectiveness and efficiency of the proposed physical fault models and algorithms.

关键词： content addressable memory test algorithm physical fault model

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FAULT-DETECTION IN TFCMOS DFCMOS COMBINATIONAL GATES

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INTEGRATION-THE VLSI JOURNAL 1993年第2期15卷 201-227页

作者： BUONANNO, G LOMBARDI, F SCIUTO, D SHEN, YN TEXAS A&M UNIV SYST DEPT COMP SCICOLL STNTX 77843

A design for testability technique and an associated test algorithm are presented for CMOS combinational circuits. It will be shown that stuck-open faults, stuck-on faults, bridging faults and delay faults can all be ... 详细信息

关键词： STUCK-OPEN AND STUCK-ON FAULTS BRIDGING FAULTS DELAYS DESIGN FOR testABILITY test algorithm FULLY CMOS COMBINATIONAL CIRCUITS

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