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A new method to evaluate interlacing yarns

TEXTILE RESEARCH JOURNAL 2020年第7-8期90卷 838-846页

作者： Wang, Meng Zhan, Yinlan Yao, Leon Ningbo Shenzhou Knitting Co Ltd 636 Fuchunjiang Rd Ningbo 315000 Zhejiang Peoples R China

The theory of purification is proposed in this article. Based on the framework of this theory, several models can be built to give a synthetic quality evaluation of interlacing yarns. In this paper, three models are given. The first one is the most popular method to evaluate the quality of interlacing yarn and we can prove it meets the theory of purification. The second one is modified according to the coefficient of variation. The third one is a new evaluation method. Meanwhile, we give a test algorithm to compare the degree of reflecting common cognition of the three models. From the result of comparison and analysis, the new evaluation method is recommended. It has a comparatively complete evaluation value for every state in universe M. Compared to other modeling methods, this method can give every level of interlacing yarn a relatively pertinent evaluation.

关键词： interlacing yarn equality evaluation theory of purification test algorithm

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testing Neighbouring Cell Leakage and Transition Induced Faults in DRAMs

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IEEE TRANSACTIONS ON COMPUTERS 2016年第7期65卷 2339-2345页

作者： Sfikas, Yiorgos Tsiatouhas, Yiorgos Univ Ioannina Dept Comp Sci & Engn POB 1186 GR-45110 Ioannina Greece

Due to their high density, modern DRAMs are very susceptible to the interactions between adjacent cells, which in turn increases the difficulty and complexity of memory testing. In this work, we studied the interaction mechanisms among neighbouring DRAM cells in order to provide an efficient testing solution. According to the open literature, there are two mechanisms responsible for this interaction: leakage currents and cell state transitions. The frequently used Coupling Fault (CF) model is inadequate to model the combined effect of these mechanisms, while testing procedures using the Neighborhood Pattern Sensitive Fault (NPSF) model are not time efficient solutions. Towards this direction, we propose a new fault model, the Neighborhood Leakage and Transition Fault (NLTF) model for DRAMs, which effectively models the faulty behavior related to neighbouring cell interference. In addition, we developed a new test algorithm which is based on the NLTF model, and provides test application time reductions ranging from 68 to 87 percent with respect to the existing testing algorithms in the literature that are capable to cover the NLTFs. Finally, the proposed algorithm is extended to cover NLTFs in word-oriented DRAMs.

关键词： DRAM testing neighborhood leakage transition fault (NLTF) model test algorithm

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Fault Modeling and testing of Resistive Nonvolatile-8T SRAMs 34

Fault Modeling and Testing of Resistive Nonvolatile-8T SRAMs

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IEEE 34th VLSI test Symposium (VTS)

作者： Li, Yu-Ting Chen, Yong-Xiao Li, Jin-Fu Natl Cent Univ Dept Elect Engn Taoyuan 320 Taiwan

ISBN: (纸本)9781467384544

In modern system-on-chips (SOCs), static power consumption represents a significant portion of the chip power. Since static random access memory (SRAM) typically occupies more than one half of the chip area, static power of a SOC is mainly constituted by the SRAMs. Resistive nonvolatile-8T (Rnv8T) SRAM has been proposed to alleviate static power and preserve data in power-down mode and provide fast power-on speed. A Rnv8T SRAM cell is composed of a 6T SRAM cell, two resistive devices, and two transistors. In this paper, we define several memristor-related faults for the Rnv8T SRAM considering electrical defects. Also, a March-like test algorithm which can cover simple SRAM faults and defined memristor-related faults are proposed. In comparison with the existing work, the proposed March-like test needs longer test time, but provides better fault coverage on the targeted faults.

关键词： Memristor nonvolatile SRAM fault model test algorithm March test

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test and Repair Methodology for FinFET-Based Memories

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IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY 2015年第1期15卷 3-9页

作者： Harutyunyan, Gurgen Tshagharyan, Grigor Zorian, Yervant Synopsys Inc Yerevan 0026 Armenia Synopsys Inc Mountain View CA 94043 USA

FinFET transistors are commonly acknowledged as the most promising technology able to play a crucial role to route the development of rapidly growing modern silicon industry. Embedded memories, based on FinFET transistors, lead to new defect types that can require new embedded test and repair solutions. To investigate FinFET-specific faults, the existing fault models and detection techniques are not enough because of the spatial structure of FinFET transistors. This paper presents the results of the comprehensive study carried out for FinFET-based memories based on a new fault modeling and test algorithm creation strategy. The proposed solution is validated on several real FinFET-based embedded memory technologies.

关键词： FinFET defect fault modeling test algorithm embedded memory

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Impact of Parameter Variations on FinFET Faults 33

Impact of Parameter Variations on FinFET Faults

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2015 IEEE 33rd VLSI test SYMPOSIUM (VTS)

作者： Harutyunyan, G. Tshagharyan, G. Zorian, Y. Synopsys Hyderabad Telangana India

ISBN: (纸本)9781479975976

The technology shrinking strategy below 20nm feature sizes adopted by the giants of the nowadays semiconductor industry has boosted the research on FinFET which is considered as an alternative to the conventional planar technology. This paper presents a comprehensive study carried out for FinFET-based memories using an advanced flow for fault modeling and test algorithm generation. Using this flow it has been shown that parameter variation (of process, voltage, temperature, frequency) has a significant impact on the fault coverage when dealing with FinFET-specific faults.

关键词： FinFET fault modeling test algorithm parameter variation embedded memory

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On Resistive Open Defect Detection in DRAMs: The Charge Accumulation Effect 20

On Resistive Open Defect Detection in DRAMs: The Charge Accu...

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20th IEEE European test Symposium (ETS)

作者： Sfikas, Yiorgos Tsiatouhas, Yiorgos Taouil, Mottaqiallah Hamdioui, Said Univ Ioannina Dept Comp Sci & Engn GR-45110 Ioannina Greece Delft Univ Technol Comp Engn Lab NL-2628 CD Delft Netherlands

ISBN: (纸本)9781479976034

The test complexity of high density DRAMs increases with technology evolution, due to a larger impact of process variation and weak defects. In particular, resistive open defects turn to be a major concern in DRAMs. Our analysis and simulation results show that an important phenomenon exists, charge accumulation, which is currently not considered in DRAM testing. Charge accumulation occurs in DRAM cells that suffer from internal resistive opens;a weak value stored at a cell is strengthened when a sequence of read operations is applied to it. Typical DRAM testing procedures (like March tests) fail to provide enhanced coverage of resistive open defects, since they do not consider charge accumulation. This paper provides an effective test algorithm that targets resistive open defects, while considering the bit-line imbalance and the charge accumulation mechanisms.

关键词： DRAM testing resistive opens test algorithm

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Automatic Control System for Memory Chips Performance in a Radiation Experiment

Automatic Control System for Memory Chips Performance in a R...

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International Siberian Conference on Control and Communications (SIBCON)

作者： Boruzdina, A. B. Orlov, A. A. Ulanova, A. V. Grigor'ev, N. G. Nikiforov, A. Y. Natl Res Nucl Univ MEPhI Moscow Engn Phys Inst Moscow Russia

ISBN: (纸本)9781479971039

The paper analyzes the effectiveness of test algorithms of different duration during the functional control of static random access memory (SRAM) during the exposure to total ionizin dose (TID). The results of experimental research SRAM chips using an automated system based on the equipment "PXI" company National Instruments, justifying the use of the test algorithms such as "MARCH" (long-10N).

关键词： PXI-7951R test algorithm memory chips

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Fault Modeling and testing of Resistive Nonvolatile-8T SRAMs

Fault Modeling and Testing of Resistive Nonvolatile-8T SRAMs

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IEEE VLSI test Symposium

作者： Yu-Ting Li Yong-Xiao Chen Jin-Fu Li Department of Electrical Engineering National Central University

ISBN: (纸本)9781467384551

关键词： Memristor Nonvolatile SRAM Fault model test algorithm March test

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test Solution for Data Retention Faults in Low-Power SRAMs

Test Solution for Data Retention Faults in Low-Power SRAMs

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Design, Automation and test in Europe Conference and Exhibition (DATE)

作者： Zordan, L. B. Bosio, A. Dilillo, L. Girard, P. Todri, A. Virazel, A. Badereddine, N. Univ Montpellier 2 CNRS LIRMM 161 Rue Ada F-34095 Montpellier 5 France Intel Mobile Commun F-06560 Sophia Antipolis France

ISBN: (纸本)9783981537000

Low-power SRAMs embed mechanisms for reducing static power consumption. When the SRAM is not accessed during a long period, it switches into an intermediate low-power mode. In this mode, a voltage regulator is used to reduce the voltage supplied to the core-cells as low as possible without data loss. Thus, faulty-free behavior of the voltage regulator is crucial for ensuring data retention in core-cells when the SRAM is in low-power mode. This paper investigates the root cause of data retention faults due to voltage regulator malfunctions. This analysis is done under realistic conditions (i.e., industrial core-cells affected by process variations). Based on this analysis, we propose an efficient test flow for detecting data retention faults in low-power SRAMs.

关键词： SRAM low-power design test algorithm memory test

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Application of Defect Injection Flow for Fault Validation in Memories

Application of Defect Injection Flow for Fault Validation in...

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IEEE East-West Design and test Symposium (EWDTS)

作者： Amirkhanyan, K. Davtyan, A. Harutyunyan, G. Melkumyan, T. Shoukourian, S. Vardanian, V. Zorian, Y. Synopsys Mountain View CA 94043 USA

ISBN: (纸本)9781479920952;9781479920969

In the paper, an advanced flow for defect injection in the memories and its application for fault validation are presented. Specifically, the results of injecting address decoder and process variation defects are illustrated. The defect injection flow gives a possibility to inject different types of defects (such as resistive opens, resistive shorts, process variation defects, etc.) in different blocks of the memory layout (memory array, address decoder, sense amplifier, etc.) and then verify if a given test algorithm detects the injected defect.

关键词： defect injection memory programming test algorithm address decoder defects process variation defects

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