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An Effective Programmable Memory BIST for Embedded Memory

IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS 2009年第12期E92D卷 2508-2511页

作者： Park, Youngkyu Park, Jaeseok Han, Taewoo Kang, Sungho Yonsei Univ Dept Elect & Elect Engn Seoul 120749 South Korea

This paper proposes a micro-code based Programmable Memory BIST (PMBIST) architecture that can support various kinds of test algorithms. The proposed Non-linear PMBIST (NPMBIST.) guarantees high flexibility and high fault coverage using not only March algorithms but also non-linear algorithms such as Walking and Galloping. This NPMBIST has an optimized hardware overhead, since algorithms can be implemented with the minimum bits by the optimized instructions. Finally, various and complex algorithms can be run thanks to its support of multi-loop.

关键词： Programmable BIST test algorithm multi-loop

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NEW algorithm FOR testING RANDOM-ACCESS MEMORIES

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ELECTRONICS LETTERS 1991年第7期27卷 574-575页

作者： RAJSUMAN, R Dept. of Comput. Eng. & Sci. Case Western Reserve Univ. Cleveland OH USA

A linear time complexity algorithm to test RAMs is presented. The algorithm requires only 7n read/write operations and provides an extensive fault coverage. The main advantage of the proposed scheme is that a small te... 详细信息

关键词： MEMORIES FAULT DETECTION test algorithm

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A new method to evaluate interlacing yarns

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TEXTILE RESEARCH JOURNAL 2020年第7-8期90卷 838-846页

作者： Wang, Meng Zhan, Yinlan Yao, Leon Ningbo Shenzhou Knitting Co Ltd 636 Fuchunjiang Rd Ningbo 315000 Zhejiang Peoples R China

The theory of purification is proposed in this article. Based on the framework of this theory, several models can be built to give a synthetic quality evaluation of interlacing yarns. In this paper, three models are given. The first one is the most popular method to evaluate the quality of interlacing yarn and we can prove it meets the theory of purification. The second one is modified according to the coefficient of variation. The third one is a new evaluation method. Meanwhile, we give a test algorithm to compare the degree of reflecting common cognition of the three models. From the result of comparison and analysis, the new evaluation method is recommended. It has a comparatively complete evaluation value for every state in universe M. Compared to other modeling methods, this method can give every level of interlacing yarn a relatively pertinent evaluation.

关键词： interlacing yarn equality evaluation theory of purification test algorithm

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testing Neighbouring Cell Leakage and Transition Induced Faults in DRAMs

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IEEE TRANSACTIONS ON COMPUTERS 2016年第7期65卷 2339-2345页

作者： Sfikas, Yiorgos Tsiatouhas, Yiorgos Univ Ioannina Dept Comp Sci & Engn POB 1186 GR-45110 Ioannina Greece

Due to their high density, modern DRAMs are very susceptible to the interactions between adjacent cells, which in turn increases the difficulty and complexity of memory testing. In this work, we studied the interaction mechanisms among neighbouring DRAM cells in order to provide an efficient testing solution. According to the open literature, there are two mechanisms responsible for this interaction: leakage currents and cell state transitions. The frequently used Coupling Fault (CF) model is inadequate to model the combined effect of these mechanisms, while testing procedures using the Neighborhood Pattern Sensitive Fault (NPSF) model are not time efficient solutions. Towards this direction, we propose a new fault model, the Neighborhood Leakage and Transition Fault (NLTF) model for DRAMs, which effectively models the faulty behavior related to neighbouring cell interference. In addition, we developed a new test algorithm which is based on the NLTF model, and provides test application time reductions ranging from 68 to 87 percent with respect to the existing testing algorithms in the literature that are capable to cover the NLTFs. Finally, the proposed algorithm is extended to cover NLTFs in word-oriented DRAMs.

关键词： DRAM testing neighborhood leakage transition fault (NLTF) model test algorithm

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Impact of Parameter Variations on FinFET Faults 33

Impact of Parameter Variations on FinFET Faults

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2015 IEEE 33rd VLSI test SYMPOSIUM (VTS)

作者： Harutyunyan, G. Tshagharyan, G. Zorian, Y. Synopsys Hyderabad Telangana India

ISBN: (纸本)9781479975976

The technology shrinking strategy below 20nm feature sizes adopted by the giants of the nowadays semiconductor industry has boosted the research on FinFET which is considered as an alternative to the conventional planar technology. This paper presents a comprehensive study carried out for FinFET-based memories using an advanced flow for fault modeling and test algorithm generation. Using this flow it has been shown that parameter variation (of process, voltage, temperature, frequency) has a significant impact on the fault coverage when dealing with FinFET-specific faults.

关键词： FinFET fault modeling test algorithm parameter variation embedded memory

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Method of Alloying Engine Oil with Complex Copper Compounds

Method of Alloying Engine Oil with Complex Copper Compounds

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Conference on Intelligent Technologies and Electronic Devices in Vehicle and Road Transport Complex (TIRVED)

作者： Ershov, V. S. Gaidar, S. M. Karelina, M. Yu Akulov, A. A. Moscow Automobile & Rd Construct State Tech Univ Moscow Russia Russian State Agr Univ Moscow Timiryazev Agr Acad Moscow Russia

ISBN: (纸本)9781665400756

This paper presents a method of alloying engine oil with complex copper compounds, which can significantly reduce wear on rubbing surfaces and increase the reliability of the internal combustion engine by transferring copper from the alloy to the surface. A device for alloying engine oil with copper-containing elements has been developed. The process of copper cladding of surfaces of movable joints of machines and mechanisms is described. The dependence between the number of copper particles in the lubricating medium, the size of the copper element area and the ligand concentration in the lubricant is revealed. The study of steel samples for corrosion resistance in different lubricating environments has been carried out. The experiment to determine the dissolution rate of copper depending on the amount of ligand in the base oil has been conducted, as well as to determine the optimal amount of copper. The article analyzes the economic effect of using a metal-plating additive (MPA) in the operation of a vehicle.

关键词： additive reliability internal combustion engine test algorithm performance improvement

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Fault Modeling and testing of Memristor-Based Spiking Neural Networks

Fault Modeling and Testing of Memristor-Based Spiking Neural...

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IEEE International test Conference (ITC)

作者： Hou, Kuan-Wei Cheng, Hsueh-Hung Tung, Chi Wu, Cheng-Wen Lu, Juin-Ming Natl Tsing Hua Univ Dept Elect Engn Hsinchu Taiwan Ind Technol Res Inst Hsinchu Taiwan

ISBN: (数字)9781665462709

ISBN: (纸本)9781665462709

The resistive random-access memory (RRAM), whose core is composed of memristor cell arrays, has recently been proposed for implementing the deep neural network (DNN) and spiking neural network (SNN), which potentially can improve the performance and energy efficiency of AI computing. In this paper, we address highquality memristor-based SNNs. We propose two functional fault models for them, i.e., the Slow Integration Fault (SIF) and Fast Integration Fault (FIF), and show the circuit-level fault simulation results, taking process variation into account. The detailed simulation and analysis results show that the SIF and FIF are feasible functional fault models for memristor-based SNNs, as the interconnect open and short defects, as well as the memristor and transistor faults, can all be covered by the proposed SIF and FIF. We have also developed a test algorithm for the SNNs, i.e., the SNN-test algorithm. Experimental results show that the SNN-test covers 100% of the open and short defects and the proposed functional fault models.

关键词： Memnistor Spiking Neural Network In-Memory Computing Fault Model Fault Simulator test algorithm

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Fault Modeling and testing of Resistive Nonvolatile-8T SRAMs 34

Fault Modeling and Testing of Resistive Nonvolatile-8T SRAMs

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IEEE 34th VLSI test Symposium (VTS)

作者： Li, Yu-Ting Chen, Yong-Xiao Li, Jin-Fu Natl Cent Univ Dept Elect Engn Taoyuan 320 Taiwan

ISBN: (纸本)9781467384544

In modern system-on-chips (SOCs), static power consumption represents a significant portion of the chip power. Since static random access memory (SRAM) typically occupies more than one half of the chip area, static power of a SOC is mainly constituted by the SRAMs. Resistive nonvolatile-8T (Rnv8T) SRAM has been proposed to alleviate static power and preserve data in power-down mode and provide fast power-on speed. A Rnv8T SRAM cell is composed of a 6T SRAM cell, two resistive devices, and two transistors. In this paper, we define several memristor-related faults for the Rnv8T SRAM considering electrical defects. Also, a March-like test algorithm which can cover simple SRAM faults and defined memristor-related faults are proposed. In comparison with the existing work, the proposed March-like test needs longer test time, but provides better fault coverage on the targeted faults.

关键词： Memristor nonvolatile SRAM fault model test algorithm March test

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On Resistive Open Defect Detection in DRAMs: The Charge Accumulation Effect 20

On Resistive Open Defect Detection in DRAMs: The Charge Accu...

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20th IEEE European test Symposium (ETS)

作者： Sfikas, Yiorgos Tsiatouhas, Yiorgos Taouil, Mottaqiallah Hamdioui, Said Univ Ioannina Dept Comp Sci & Engn GR-45110 Ioannina Greece Delft Univ Technol Comp Engn Lab NL-2628 CD Delft Netherlands

ISBN: (纸本)9781479976034

The test complexity of high density DRAMs increases with technology evolution, due to a larger impact of process variation and weak defects. In particular, resistive open defects turn to be a major concern in DRAMs. Our analysis and simulation results show that an important phenomenon exists, charge accumulation, which is currently not considered in DRAM testing. Charge accumulation occurs in DRAM cells that suffer from internal resistive opens;a weak value stored at a cell is strengthened when a sequence of read operations is applied to it. Typical DRAM testing procedures (like March tests) fail to provide enhanced coverage of resistive open defects, since they do not consider charge accumulation. This paper provides an effective test algorithm that targets resistive open defects, while considering the bit-line imbalance and the charge accumulation mechanisms.

关键词： DRAM testing resistive opens test algorithm

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Automatic Control System for Memory Chips Performance in a Radiation Experiment

Automatic Control System for Memory Chips Performance in a R...

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International Siberian Conference on Control and Communications (SIBCON)

作者： Boruzdina, A. B. Orlov, A. A. Ulanova, A. V. Grigor'ev, N. G. Nikiforov, A. Y. Natl Res Nucl Univ MEPhI Moscow Engn Phys Inst Moscow Russia

ISBN: (纸本)9781479971039

The paper analyzes the effectiveness of test algorithms of different duration during the functional control of static random access memory (SRAM) during the exposure to total ionizin dose (TID). The results of experimental research SRAM chips using an automated system based on the equipment "PXI" company National Instruments, justifying the use of the test algorithms such as "MARCH" (long-10N).

关键词： PXI-7951R test algorithm memory chips

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