In this paper, we presented algorithms for testing gain error, offset error, differential nonlinearity (DNL) and integral nonlinearity (INL) of analog-to -digital converters (ADC), and proposed an easily integrated bu...
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ISBN:
(纸本)078038511X
In this paper, we presented algorithms for testing gain error, offset error, differential nonlinearity (DNL) and integral nonlinearity (INL) of analog-to -digital converters (ADC), and proposed an easily integrated built-in self-test (BIST) scheme on chip, which has been designed using Chartered 0.35 mu m technology. The experimental results show that the proposed BIST scheme has low area overhead, low test cost and high test accuracy.
In the paper, an advanced flow for defect injection in the memories and its application for fault validation are presented. Specifically, the results of injecting address decoder and process variation defects are illu...
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ISBN:
(纸本)9781479920952;9781479920969
In the paper, an advanced flow for defect injection in the memories and its application for fault validation are presented. Specifically, the results of injecting address decoder and process variation defects are illustrated. The defect injection flow gives a possibility to inject different types of defects (such as resistive opens, resistive shorts, process variation defects, etc.) in different blocks of the memory layout (memory array, address decoder, sense amplifier, etc.) and then verify if a given test algorithm detects the injected defect.
Delay testing has become an area of focus in the field of digital circuits as the speed and density of circuits have greatly improved. This paper proposes a new scan flip-flop and test algorithm to overcome some of th...
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Delay testing has become an area of focus in the field of digital circuits as the speed and density of circuits have greatly improved. This paper proposes a new scan flip-flop and test algorithm to overcome some of the problems in delay testing. In the proposed test algorithm, the second test pattern is generated by scan justification, and the first test pattern is processed by functional justification. In the conventional functional justification, it is hard to generate the proper second test pattern because it uses a combinational circuit for the pattern. The proposed scan justification has the advantage of easily generating the second test pattern by direct justification from the scan. To implement our scheme, we devised a new scan in which the slave latch is bypassed by an additional latch to allow the slave to hold its state while a new pattern is scanned in. Experimental results on ISCAS'89 benchmark circuits show that the number of testable paths can be increased by about 45% over the conventional functional justification.
Background: Feature gene extraction is a fundamental issue in microarray-based biomarker discovery. It is normally treated as an optimization problem of finding the best predictive feature genes that can effectively a...
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Background: Feature gene extraction is a fundamental issue in microarray-based biomarker discovery. It is normally treated as an optimization problem of finding the best predictive feature genes that can effectively and stably discriminate distinct types of disease conditions, e.g. tumors and normals. Since gene microarray data normally involves thousands of genes at, tens or hundreds of samples, the gene extraction process may fall into local optimums if the gene set is optimized according to the maximization of classification accuracy of the classifier built from it. Results: In this paper, we propose a novel gene extraction method of error margin analysis to optimize the feature genes. The proposed algorithm has been tested upon one synthetic dataset and two real microarray datasets. Meanwhile, it has been compared with five existing gene extraction algorithms on each dataset. On the synthetic dataset, the results show that the feature set extracted by our algorithm is the closest to the actual gene set. For the two real datasets, our algorithm is superior in terms of balancing the size and the validation accuracy of the resultant gene set when comparing to other algorithms. Conclusion: Because of its distinct features, error margin analysis method can stably extract the relevant feature genes from microarray data for high-performance classification.
In this paper,we presented algorithms for testing gain error,offset error,differential nonlinearity(DNL) and integral nonlinearity(INL)of analog-to-digital converters(ADC),and proposed an easily integrated built-in se...
详细信息
In this paper,we presented algorithms for testing gain error,offset error,differential nonlinearity(DNL) and integral nonlinearity(INL)of analog-to-digital converters(ADC),and proposed an easily integrated built-in self-test(BIST)scheme on chip,which has been designed using Chartered 0.35μm *** experimental results show that the proposed BIST scheme has low area overhead,low test cost and high test accuracy.
In modern system-on-chips (SOCs), static power consumption represents a significant portion of the chip power. Since static random access memory (SRAM) typically occupies more than one half of the chip area, static po...
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ISBN:
(纸本)9781467384551
In modern system-on-chips (SOCs), static power consumption represents a significant portion of the chip power. Since static random access memory (SRAM) typically occupies more than one half of the chip area, static power of a SOC is mainly constituted by the SRAMs. Resistive nonvolatile-8T (Rnv8T) SRAM has been proposed to alleviate static power and preserve data in power-down mode and provide fast power-on speed. A Rnv8T SRAM cell is composed of a 6T SRAM cell, two resistive devices, and two transistors. In this paper, we define several memristor-related faults for the Rnv8T SRAM considering electrical defects. Also, a March-like test algorithm which can cover simple SRAM faults and defined memristor-related faults are proposed. In comparison with the existing work, the proposed March-like test needs longer test time, but provides better fault coverage on the targeted faults.
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