With the growth in size and complexity of integrated circuits, testgeneration for them is becoming increasingly difficult, so it is important to find new and effective digital integrated circuit testgeneration algor...
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With the growth in size and complexity of integrated circuits, testgeneration for them is becoming increasingly difficult, so it is important to find new and effective digital integrated circuit test generation algorithm. In order to improve the quality of combinational testgeneration, a combinational circuits test generation algorithm based three-valued neural networks [1] is proposed in this paper. This algorithm does not need propagation and backtracks, but represents the combinational circuits as a bidirectional network of neurons using the three-valued neural networks, and constructs the energy function for the network. The application of three-valued neural works may reduce research space and avoid many wasteful assignments, improve the efficiency of combinational testgeneration. A genetic algorithm was used to find the global minimal as the test vectors. So the problem of the combinational testgeneration was formulated to an optimization problem. The experimental results on some standard circuits demonstrate that the algorithm have high fault coverage and short test time.
It is more and more important for the transient current (IDDT) test have become the complement method of voltage test and leakage current (IDDQ) test. Two kinds of IDDT module such as open fault module and delay fault...
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It is more and more important for the transient current (IDDT) test have become the complement method of voltage test and leakage current (IDDQ) test. Two kinds of IDDT module such as open fault module and delay fault module are given in this paper. The selection of testgeneration patterns for the open fault module is given, too. In the final, IDDT testgeneration arithmetic is discussed.
Many approaches, to generating a test from an FSM M, are based aroundproducing a test sequence that contains some set T of predefined sequences that, between them, testthe transitions of M. In some cases, in order to ...
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Many approaches, to generating a test from an FSM M, are based aroundproducing a test sequence that contains some set T of predefined sequences that, between them, testthe transitions of M. In some cases, in order to include each element of T it is necessary to useresets. The use of resets may increase the cost of testing and reduce the effectiveness of *** paper has considered the problem of producing a test sequence that contains the elements of Twhile using as few resets as possible. The paper has introduced an algorithm that represents theoptimization problem in terms of the Rural Chinese Postman Problem (RCPP). Since the RCPP isNP-hard, a heuristic is adapted. The resultant polynomial time algorithm is guaranteed to minimizethe number of resets used, when overlap between the elements of T is not utilized. Sometimes,overlap can be used to further reduce the number of resets. Future work will consider how overlapmay be incorporated.
A new algorithm has been developed to perform efficient delay testing. The algorithm enables applications of a new implication of value using indirect implication. The results of ISCAS benchmark circuits show the effe...
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A new algorithm has been developed to perform efficient delay testing. The algorithm enables applications of a new implication of value using indirect implication. The results of ISCAS benchmark circuits show the effectiveness of the new algorithm.
This paper presents an efficient sequential circuit automatic test generation algorithm. The algorithm is based on PODEM and uses a nine-valued logic model. Among the novel features or the algorithm are use or Initial...
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This paper presents an efficient sequential circuit automatic test generation algorithm. The algorithm is based on PODEM and uses a nine-valued logic model. Among the novel features or the algorithm are use or Initial Timeframe algorithm and correct implementation of a solution to the Previous State Information Problem. The Initial Timeframe algorithm, one of the most important aspects of the test generator, determines the number of timeframes required to excite the fault for which a test is to be derived and the number of timeframes required to observe the excited fault. Correct determination of the number of timeframes in which the fault should be excited (activated) and observed saves the test generator from performing unnecessary search in the input space. testgeneration is unidirectional, i.e., it is done strictly in forward time, and flip-flops in the initial timeframe am never assigned a state that needs to be justified later. The algorithm saves both the good and the faulty machine states after finding a test to aid in subsequent testgeneration. The Previous State Information Problem, which has often been ignored by existing test generators, is presented and discussed in the paper. Experimental results are presented to demonstrate the effectiveness of the algorithm.
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