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A built-in self-reconfigurable scheme for 3D mesh arrays

IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS 1999年第12期E82D卷 1554-1562页

作者： Takanami, I Horita, T Iwate Univ Fac Engn Morioka Iwate 0208551 Japan

We propose a model for fault tolerant 3D processor arrays using one-and-half track switches. Spare processors are laid on the two opposite surfaces of the 3D array. The fault compensation process is performed by shifting processors on a continuous straight line (called compensation path) from a faulty processor to a spare on the surfaces. It is not allowed that compensantion paths are in the near-miss relation each other [2]. Then, switches with only 4 states are needed to preserve the 3D mesh topology after compensating for faults. We give an algorithm in a convenient form for reconfiguring by hardware the 3D mesh arrays with faults. The algorithm can reconfigure the 3D mesh arrays in polynomial time. By computer simulation, we show the survival rates and the reliabilities of arrays which express the efficiencies of reconfiguration according to the algorithm. The reliabilities are compared with those of the model using double tracks far which the near-miss relation among compensation paths is allowed, but whose hardware overhead is almost double of that of the proposed model using one-and-half track. Finally, we design a logical circuit for hardware realization of the algorithm. Using the circuit, we can construct such a built-in self-reconfigurable 3D mesh array that the reconfiguration is done very quickly without an aid of a host computer.

关键词： fault tolerance reconstruction three-dimensional mesh array self-reconstruction hardware algorithm

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A PARALLEL ALGORITHM FOR FINDING THE MAXIMUM VALUE

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PARALLEL COMPUTING 1989年第1期10卷 101-108页

作者： HORIGUCHI, S MIRANKER, WL IBM Thomas J. Watson Research Center Yorktown Heights NY 10598 U.S.A.

A new parallel algorithm for finding the maximum value of a data set is proposed. Execution times are investigated by taking into account the effect of the overhead time of communication for four kinds of interconnection networks; cube connection array, linear array, mesh array, and three-dimensional mesh array. The optimal numbers of processors are derived in the case where the number of processors is less than the number of data. Those are O (N 1 2 ), O (N 2 3 ), O (N 3 4 ), and O (N) , respectively, for linear array, mesh array, three-dimensional mesh array, and cube-connected arrays.

关键词： cube-connection array execution time investigation finding the maximum value interconnection networks linear array mesh array Parallel algorithm three-dimensional mesh array

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Self-reconstruction of 3D mesh arrays with 11/2-track switches by digital neural circuits

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IEICE TRANSACTIONS ON ELECTRONICS 1999年第9期E82C卷 1678-1686页

作者： Takanami, I Nakamura, S Horita, T Iwate Univ Fac Engn Morioka Iwate 0208551 Japan ICS Co Morioka Iwate 0208544 Japan

Using Hopfield-type neural network model, we present an algorithm for reconstructing 3D mesh processor arrays using single-track switches where spare processors are laid on the six surfaces of a 3D array and show its effectiveness in terms of reconstruction rate and computing time by computer simulation. Next, we show how the algorithm can be realized by a digital neural circuit. It consists of subcircuits for finding candidate compensation paths, deciding whether the neural system reaches a stable state and at the time the system energy is minimum, and subcircuits for neurons. The subcircuit for each neuron including the other subcircuits can only be made with 16 gates and two flip-flops. Since the state transitions are done in parallel, the circuit will be able to find a set of compensation paths for a fault pattern very quickly within a time less than l mu s. Furthermore, the hardware implementation of the algorithm leads to making a self-reconfigurable system without the aid of a host computer.

关键词： fault tolerance three-dimensional mesh array self-reconstruction neural algorithm neural circuit

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