This paper proposes a time-domainanalog calculations model based on a pulse-width modulation (PWM) approach for neural network calculations including weighted-sum or multiply-and-accumulate calculation and rectified-...
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This paper proposes a time-domainanalog calculations model based on a pulse-width modulation (PWM) approach for neural network calculations including weighted-sum or multiply-and-accumulate calculation and rectified-linear unit operation. We also propose very-large-scale integration (VLSI) circuits to implement the proposed model. Unlike the conventional analog voltage or current mode circuits, our circuits use transient operation in charging/discharging processes to capacitors through resistors. Since the circuits calculate multiple weighted-sums by charging a capacitance, they can be operated with extremely low energy consumption. However, because a relatively long time constant is required to guarantee calculation resolution in the timedomain, they have to use very high-resistance devices, on the order of giga-ohms. We designed, fabricated, and tested a proof-of-concept complementary metal-oxide-semiconductor (CMOS) VLSI chip using a 250-nm fabrication technology to verify weighted-sum operation based on the proposed model with binary weights and PWM input signals, which realizes the BinaryConnect model. In the chip, memory cells of static-random-access memory (SRAM) are used for synaptic connection weights. High-resistance operation was realized by using the subthreshold operation region of MOS transistors, unlike in the ordinary in-memory-computing circuits. We evaluated the energy efficiency and temperature characteristics by measurement using the fabricated chip, where the highest energy efficiency for the weighted-sum calculation was 300 TOPS/W (Tera-Operations Per Second per Watt). The effects by a temperature change can be compensated for by adjusting the bias voltage. If state-of-the-art VLSI technology is used to implement the proposed model, an energy efficiency of more than 1,000 TOPS/W will be possible.
time-domain analog computing with transient states (TACT) approaches have been proposed to realize high performance artificial intelligence (AI) processors, which have over 100 times higher energy efficiency than the ...
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time-domain analog computing with transient states (TACT) approaches have been proposed to realize high performance artificial intelligence (AI) processors, which have over 100 times higher energy efficiency than the latest digital AI processors. Such approaches require analog memory devices that can hold and control very high resistance on the order of giga-ohms to tera-ohms, with nonvolatility and rectification. Memory devices with a field-effect transistor (FET) structure can operate in a subthreshold region to realize such high resistance, and can also rectify the current using FET operation. In this paper, we propose using ferroelectric-gate FETs (FeFETs) as a candidate for such devices. We design crossbar circuit architectures for using them, and show measurement results for device characteristics as analog memory devices with pulse control based on TACT approaches, and evaluation results for weighted-sum calculation operation in proof-of-concept FeFET circuits.
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