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Low-Cost Sorting Network Circuits Using Unary Processing

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2018年第8期26卷 1471-1480页

作者： Najafi, M. Hassan Lilja, David. J. Riedel, Marc D. Bazargan, Kia Univ Minnesota Dept Elect & Comp Engn Minneapolis MN 55455 USA

Sorting is a common task in a wide range of applications from signal and image processing to switching systems. For applications that require high performance, sorting is often performed in hardware with application-specified integrated circuits or field-programmable gate arrays. Hardware cost and power consumption are the dominant concerns. The usual approach is to wire up a network of compare-and-swap units in a configuration called the Batcher (or bitonic) network. Such networks can readily be pipelined. This paper proposes a novel area-efficient and power-efficient approach to sorting networks, based on "unary processing." In unary processing, numbers are encoded uniformly by a sequence of one value (say 1) followed by a sequence of the other value (say 0) in a stream of 0's and 1's with the value defined by the fraction of 1's in the stream. Synthesis results of complete sorting networks show up to 92% area and power saving compared to the conventional binary implementations. However, the latency increases. To mitigate the increased latency, this paper uses a novel time-encoding of data. The approach is validated with two implementations of an important application of sorting: median filtering. The result is a low cost, energy-efficient implementation of median filtering with only a slight accuracy loss, compared to conventional implementations.

关键词： Low cost design median filtering sorting networks stochastic computing time-encoding data unary processing

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Power and Area Efficient Sorting Networks using Unary Processing 35

Power and Area Efficient Sorting Networks using Unary Proces...

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35th IEEE International Conference on Computer Design (ICCD)

作者： Najafi, M. Hassan Lilja, David J. Riedel, Marc Bazargan, Kia Univ Minnesota Dept Elect & Comp Engn Minneapolis MN 55455 USA

ISBN: (纸本)9781538622544

Sorting is a common task in a wide range of applications from signal and image processing to switching systems. For applications that require high performance, sorting is often performed in hardware. Hardware cost and power consumption are the dominant concerns. The usual approach is to wire up a network of compare-and-swap units in a configuration called a Batcher (or Bitonic) network. This paper proposes a novel area- and power-efficient approach to sorting networks based on "unary processing." data is encoded as serial bit-streams, with values represented by the fraction of 1's in a stream of 0's and 1's. (This is an evolution of prior work on stochastic logic. Unlike stochastic logic, the unary approach is deterministic and completely accurate.) Synthesis results of complete sorting networks show up to 87% area and power saving compared to the conventional binary implementations. However, the latency increases. To mitigate the increased latency, the paper uses a novel time-encoding of data. The approach is validated with implementation of an important application of sorting: median filtering. The result is a low-cost, energy-efficient implementation of median filtering with only a slight accuracy loss.

关键词： Sorting networks unary processing time-encoding data stochastic computing median filtering low-cost design

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