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Conference on VLSI Circuits and Systems

作者： Chen, XY Yao, QD Liu, P Zhejiang Univ Dept Info Sci & Electron Engn Hangzhou 310027 Peoples R China

ISBN: (纸本)0819449776

turbo codes are now universally known as one of the most effective techniques for achieving performance very close to the Shannon theoretical limits in many transmission systems. This paper presents a hardware turbo decoder core's design, The proposed architectures achieve an complexity reduction. Large memories is avoid by using sliding window(SW) algorithm, the lossless data compression is also contribute to memories reduction. The learning period is add to turn away the SNR loss due to the SW. This core is fit to realize not only in FPGA, but also can embedded into other DSP and the process rate can reach 4Mbps.

关键词： turbo decoder sliding window Log-Map

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turbo NOC: A Framework for the Design of Network-on-Chip-Based turbo decoder Architectures

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2010年第10期57卷 2776-2789页

作者： Martina, Maurizio Masera, Guido Politecn Torino Dipartimento Elettron I-10129 Turin Italy

This paper proposes a general framework for the design and simulation of network-on-chip-based turbo decoder architectures. Several parameters in the design space are investigated, namely, network topology, parallelism degree, the rate at which messages are sent by processing nodes over the network, and routing strategy. The main results of this analysis are as follows: 1) the most suited topologies to achieve high throughput with a limited complexity overhead are generalized de Bruijn and generalized Kautz topologies and 2) depending on the throughput requirements, different parallelism degrees, message injection rates, and routing algorithms can be used to minimize the network area overhead.

关键词： Network on chip (NOC) turbo decoder VLSI

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Parallel Interleaver Design for a High Throughput HSPA plus /LTE Multi-Standard turbo decoder

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2014年第5期61卷 1376-1389页

作者： Wang, Guohui Shen, Hao Sun, Yang Cavallaro, Joseph R. Vosoughi, Aida Guo, Yuanbin Rice Univ Dept Elect & Comp Engn Houston TX 77005 USA Futurewei Technol US Res Ctr Wireless R&D Plano TX 75024 USA

To meet the evolving data rate requirements of emerging wireless communication technologies, many parallel architectures have been proposed to implement high throughput turbo decoders. However, concurrent memory reading/writing in parallel turbo decoding architectures leads to severe memory conflict problem, which has become a major bottleneck for high throughput turbo decoders. In this paper, we propose a flexible and efficient VLSI architecture to solve the memory conflict problem for highly parallel turbo decoders targeting multi-standard 3G/4G wireless communication systems. To demonstrate the effectiveness of the proposed parallel interleaver architecture, we implemented an HSPA+/LTE/LTE-Advanced multi-standard turbo decoder with a 45 nm CMOS technology. The implemented turbo decoder consists of 16 Radix-4 MAP decoder cores, and the chip core area is 2.43 mm(2). When clocked at 600 MHz, this turbo decoder can achieve a maximum decoding throughput of 826 Mbps in the HSPA+ mode and 1.67 Gbps in the LTE/LTE-Advanced mode, exceeding the peak data rate requirements for both standards.

关键词： ASIC implementation HSPA interleaver LTE/LTE-advanced memory contention parallel processing turbo decoder VLSI architecture

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A state metrics compressed decoding technique for energy-efficient turbo decoder

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EURASIP JOURNAL ON WIRELESS COMMUNICATIONS AND NETWORKING 2018年第1期2018卷 1页

作者： Zhan, Ming Pang, Zhibo Xiao, Ming Wen, Hong Univ Chongqing Coll Elect & Informat Engn Southwest Univ Key Lab Networks & Cloud Comp Secur Chongqing 400715 Peoples R China ABB Corp Res Forskargrand 7 SE-72178 Vasteras Sweden KTH Royal Inst Technol Sch Elect Engn SE-10044 Stockholm Sweden Univ Elect Sci & Technol China Natl Key Lab Sci & Technol Commun Chengdu 611731 Sichuan Peoples R China

In the energy resource-constrained wireless applications, turbo codes are frequently employed to guarantee reliable data communication. To both reduce the power dissipation of the turbo decoder and the probability of data frame retransmission in the physical layer, memory capacity reduced near optimal turbo decoder is of special importance from the perspective of practical implementation. In this regard, a state metrics compressed decoding technique is proposed. By inserting two modules in the conventional turbo decoding architecture, a smaller quantization scheme can be applied to the compressed state metrics. Furthermore, structure of the inserted modules is described in detail. We demonstrate that one or two rounds of compression/decompression are performed in most cases during the iterative decoding process. At the cost of limited dummy decoding complexity, the state metrics cache (SMC) capacity is reduced by 53.75%. Although the proposed technique is a lossy compression strategy, the introduced errors only have tiny negative influence on the decoding performance as compared with the optimal Log-MAP algorithm.

关键词： Energy efficiency turbo decoder State metrics SMC capacity Compression Decompression

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Reconfigurable turbo decoder With Parallel Architecture for 3GPP LTE System

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2010年第7期57卷 566-570页

作者： Wong, Cheng-Chi Chang, Hsie-Chia Natl Chiao Tung Univ Dept Elect Engn Hsinchu 300 Taiwan Natl Chiao Tung Univ Inst Elect Hsinchu 300 Taiwan

This brief presents a parallel architecture for the turbo decoder using the quadratic permutation polynomial inter-leaver. The supported block size ranges from 40 to 6144 with an increment of 8, and thus, it includes 188 sizes in the 3rd Generation Partnership Project Long Term Evolution standard. The proposed design can allow one, two, four, or eight soft-in/soft-out decoders to process each block with configurable iterations. To support all data transmissions in the parallel design, a multistage network with low complexity is also utilized. Moreover, a robust path metric initialization is given to improve the performance loss in small blocks and high parallelism. After fabrication in the 90-nm process, the 2.1-mm(2) chip can achieve 130 Mb/s with 219 mW for the size-6144 block and eight iterations.

关键词： 3rd Generation Partnership Project (3GPP) Long Term Evolution (LTE) quadratic permutation polynomial (QPP) interleaver turbo decoder

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Improving Network-on-Chip-based turbo decoder Architectures

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JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 2013年第1期73卷 83-100页

作者： Martina, Maurizio Masera, Guido Politecn Torino Dipartimento Elettron & Telecomunicaz I-10129 Turin Italy

In this work novel results concerning Network-on-Chip-based turbo decoder architectures are presented. Stemming from previous publications, this work concentrates first on improving the throughput by exploiting adaptive-bandwidth-reduction techniques. This technique shows in the best case an improvement of more than 60 Mb/s. Moreover, it is known that double-binary turbo decoders require higher area than binary ones. This characteristic has the negative effect of increasing the data width of the network nodes. Thus, the second contribution of this work is to reduce the network complexity to support double-binary codes, by exploiting bit-level and pseudo-floating-point representation of the extrinsic information. These two techniques allow for an area reduction of up to more than the 40 % with a performance degradation of about 0.2 dB.

关键词： NoC turbo decoder VLSI

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Reverse Calculation-Based Low Memory turbo decoder for Power Constrained Applications

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2021年第6期68卷 2688-2701页

作者： Zhan, Ming Pang, Zhibo Yu, Kan Wen, Hong Southwest Univ Coll Elect & Informat Engn Chongqing 400715 Peoples R China ABB Corp Res S-72226 Vasteras Sweden KTH Royal Inst Technol Dept Intelligent Syst S-11428 Stockholm Sweden La Trobe Univ Bendigo Sch Engn & Math Sci Dept Comp Sci & Informat Technol Flora Hill Vic 3552 Australia Univ Elect Sci & Technol China UESTC Sch Aeronaut & Astronaut Chengdu 611731 Peoples R China

turbo codes are a family of near Shannon limit error correction coding schemes that usually are adopted for wireless data transmission. To reduce the power dissipation of a long-term evolution (LTE) advanced turbo decoder, in this paper, we propose a reverse calculation based low memory turbo decoder architecture by partitioning the trellis diagram and simplifying the max* operator. The designed forward state metrics calculation architecture is merged with two classical decoding schemes. Through field programmable gate array (FPGA) hardware implementation, the state metrics cache (SMC) capacity is reduced by 65%, the power dissipation of the reverse calculation architecture is significantly reduced for all tested clock frequencies, and the decoding performance is not affected as compared with classical decoding schemes. The proposed reverse calculation architecture is an effective technique to achieve better decoding performance for power-constrained applications.

关键词： LTE-Advanced standard turbo decoder state metrics SMC capacity reverse calculation power dissipation

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Development of 100 MHz Bandwidth Testbed toward IMT-Advanced and Experimental Results Including Rotational OFDM and Twin turbo decoder Transmission Performances

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IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES 2009年第9期E92A卷 2209-2217页

作者： Miyazaki, Noriaki Hatakawa, Yasuyuki Suzuki, Toshinori KDDI R&D Labs Fujimino 3568502 Japan

Aiming at actual evaluation of IMT-Advanced system performance using field tests, this paper develops an IMT-Advanced testbed system with a transmission bandwidth of 100 MHz. Taking into account recent advances in research and development of an IMT-Advanced system, orthogonal frequency division multiplexing (OFDM) with multiple-input multiple-output (MIMO) are also promising technologies in IMT-Advanced. In addition, in order to meet the requirements for IMT-Advanced, the system seems to have a bandwidth of about 100 MHz with the aid of MIMO transmission. The developed system is based on the above more reliable prediction compared with previous studies, and the goals of this development are to provide a more realistic transmission performance, judgment criteria for operators introducing new air interfaces, and to explore new applications. This paper also presents the experimental results of rotational OFDM (R-OFDM) and twin turbo (T2) decoder implemented in the testbed and demonstrates that our proposals are better than the conventional schemes in actual radio transmission. Both physical layer technologies have been proposed by the authors, however, the previous works are only predicated on computer simulation. In this paper, the proposals are experimentally evaluated by distorting the transmitted signal on radio waves with a fading simulator and additional noise generator. When the packet error rate performance is measured, the measurement results are verified to be in good agreement with the simulation results. The experimental results also demonstrate that the R-OFDM can reduce the required carrier to the interference power ratio (CIR) of OFDM by about 1.1 dB in single-input single output (SISO) multi-path fading channel. In addition, it becomes clear that the T2 decoder is better than the turbo decoder in error correction, and the required CIR reduction achieves about 0.8 dB in SISO AWGN channel. The throughput performances are also measured with different modul

关键词： IMT-Advanced E-UTRA testbed experimental results OFDM turbo decoder

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Design and implementation of a turbo decoder for 3G W-CDMA systems

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IEEE TRANSACTIONS ON CONSUMER ELECTRONICS 2002年第2期48卷 284-291页

作者： Zeng, XJ Hong, ZL Fudan Univ Dept Elect Engn Shanghai 200433 Peoples R China

This paper presents the design and hardware implementation of a log-MAP turbo decoder used in the third generation (3 G) mobile communication W-CDMA systems. The decoding algorithm is highly data dominated and needs many memories for data storing. The memory requirements are systematically investigated and optimized from the two aspects: (1) an alternative called state metric difference-storing method is proposed to save the forward state metric (alpha) and the backward state metric (beta) memory up to 1/3, (2) the interleaver address memory is reduced by repeating the address calculation at each iteration. The experimental results on an FPGA prototype of the decoder show that it supports 2Mbits/s data rate with five iterations, and for code blocks of more than 2000, a bit error rate (BER) of 10(-6)-10(-7) is achieved at E-b/N-o=1.0dB after only five iterations.

关键词： turbo decoder log-MAP iterative decoding W-CDMA

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A Flexible LDPC/turbo decoder Architecture

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JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 2011年第1期64卷 1-16页

作者： Sun, Yang Cavallaro, Joseph R. Rice Univ Dept Elect & Comp Engn Houston TX 77005 USA

Low-density parity-check (LDPC) codes and convolutional turbo codes are two of the most powerful error correcting codes that are widely used in modern communication systems. In a multi-mode baseband receiver, both LDPC and turbo decoders may be required. However, the different decoding approaches for LDPC and turbo codes usually lead to different hardware architectures. In this paper we propose a unified message passing algorithm for LDPC and turbo codes and introduce a flexible soft-input soft-output (SISO) module to handle LDPC/turbo decoding. We employ the trellis-based maximum a posteriori (MAP) algorithm as a bridge between LDPC and turbo codes decoding. We view the LDPC code as a concatenation of n super-codes where each super-code has a simpler trellis structure so that the MAP algorithm can be easily applied to it. We propose a flexible functional unit (FFU) for MAP processing of LDPC and turbo codes with a low hardware overhead (about 15% area and timing overhead). Based on the FFU, we propose an area-efficient flexible SISO decoder architecture to support LDPC/turbo codes decoding. Multiple such SISO modules can be embedded into a parallel decoder for higher decoding throughput. As a case study, a flexible LDPC/turbo decoder has been synthesized on a TSMC 90 nm CMOS technology with a core area of 3.2 mm(2). The decoder can support IEEE 802.16e LDPC codes, IEEE 802.11n LDPC codes, and 3GPP LTE turbo codes. Running at 500 MHz clock frequency, the decoder can sustain up to 600 Mbps LDPC decoding or 450 Mbps turbo decoding.

关键词： SISO decoder LDPC decoder turbo decoder Error correcting codes MAP algorithm Reconfigurable architecture

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