检索结果-内蒙古大学图书馆

Simple super-matrix processor: Implementation and performance evaluation

JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING 2015年 83卷 96-118页

作者： Soliman, Mostafa I. Elsayed, Elsayed A. Taibah Univ Dept Informat & Comp Sci Community Coll Al Madinah Al Munawwarah Saudi Arabia Aswan Univ Dept Elect Engn Fac Engn Comp & Syst Sect Aswan 81542 Egypt

Data-parallel applications are growing in importance and demanding increased performance from hardware. Since the fundamental data structures for a wide variety of data parallel applications are scalar, vector, and matrix, this paper proposes a simple matrix processor (SMP) for executing scalar, vector, and matrix instructions on a unified datapath. matrix register file and matrix control unit are added to the decode stage of the well-known 5-stage pipeline (baseline scalar processor). To further improve the performance, a simple super-matrix processor (SSMP) is proposed to execute multi-scalar/vector/matrix instructions on parallel execution datapaths. 4 x 32-bit instructions are fetched, decoded, and checked for dependencies. Up to four independent scalar instructions can be issued in-order to the parallel execution units. However, vector/matrix instructions iterate the issuing of four vector/matrix operations without checking. 4 x 32-bit contiguous vector/matrix elements can be loaded/stored per clock cycle from/to L2 cache to/from matrix register file, however, scalar data can be accessed from L1 cache in a rate of one element per clock cycle. To prove our concept, the proposed SMP/SSMP are implemented on Xilinx Virtex-6 and evaluated on vector/matrix kernels. 8679/11734 slices are required for implementing SMP/SSMP, where the complexities are 2.79/3.77 times higher than the baseline scalar processor. However, the speedups of SMP/SSMP over the baseline scalar processor are 1.57-6.33/4.32-18.23. (C) 2015 Elsevier Inc. All rights reserved.

关键词： FPGA implementation Data-parallel applications vector/matrix processing Performance evaluation

来源：评论

学校读者我要写书评

暂无评论

A highly efficient implementation of a backpropagation learning algorithm using matrix ISA

引用

JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING 2008年第7期68卷 949-961页

作者： Soliman, Mostafa I. Mohamed, Samir A. S Valley Univ Comp & Control Sect Dept Elect Engn Fac Engn Aswan Egypt

BackPropagation (BP) is the most famous learning algorithm for Artificial Neural Networks (ANN). BP has received intensive research efforts to exploit its parallelism in order to reduce the training time for complex problems. A modified version of BP based on matrix-matrix multiplication was proposed for parallel processing. In this paper, we present the implementation of matrix BackPropagation (MBP) using scalar, vector, and matrix Instruction Set Architectures (ISAs). Besides this, we show that the performance of the MBP is improved by switching from scalar ISA to vector ISA. It is further improved by switching from vector ISA to matrix ISA. On a practical application, speech recognition, the speedup of training a neural network using unrolling scalar ISA over scalar ISA is 1.83. On eight parallel lanes, the speedups of using vector, unrolling vector, and matrix ISAs are respectively 10.33, 11.88, and 15.36, where the maximum theoretical speedup is 16. The results obtained show that the use of matrix ISA gives a performance close to optimal, because of reusing the loaded data, decreasing the loop overhead, and overlapping the memory operations with arithmetic operations. (c) 2008 Elsevier Inc. All rights reserved.

关键词： neural networks parallel architecture vector/matrix processing parallel algorithms backpropagation algorithm reusing data loop unrolling

来源：评论

学校读者我要写书评

暂无评论

A shared matrix unit for a chip multi-core processor

引用

JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING 2013年第8期73卷 1146-1156页

作者： Soliman, Mostafa I. Al-Junaid, Abdulmajid F. Aswan Univ Fac Engn Dept Elect Engn Comp & Syst Sect Aswan 81542 Egypt Ibb Univ Fac Engn & Architecture Dept Elect Engn Ibb Yemen

This paper proposes extending a multi-core processor with a common matrix unit to maximize on-chip resource utilization and to leverage the advantages of the current multi-core revolution to improve the performance of data-parallel applications. Each core fetches scalar/vector/matrix instructions from its instruction cache. Scalar instructions continue the execution on the scalar datapath;however, vector/matrix instructions are issued by the decode stage to the shared matrix unit through the corresponding FIFO queue. Moreover, scalar results from reduction vector/matrix instructions are sent back from the matrix unit to the scalar core that sent these instructions. Some dense linear algebra kernels (scalar-vector multiplication, scalar times vector plus another, apply Givens rotation, rank-1 update, vector-matrix multiplication, and matrix-matrix multiplication) as well as discrete cosine transform, sum of absolute differences, and affine transformation are used in the performance evaluation. Our results show that the improvement in the utilization of the shared matrix unit with a dual-core ranges from 9% to 26% compared to extending a matrix unit to a single-core. Moreover, the average speedup of the dual-core shared matrix unit over a single-core extended with a matrix unit ranges from 6% to 24% and the maximum speedup ranges from 13% to 46%. (C) 2013 Elsevier Inc. All rights reserved.

关键词： SystemC implementation Multi-core processors Parallel processing vector/matrix processing

来源：评论

学校读者我要写书评

暂无评论

SYSTEMC IMPLEMENTATION AND PERFORMANCE EVALUATION OF A DECOUPLED GENERAL-PURPOSE matrix PROCESSOR

引用

PARALLEL processing LETTERS 2010年第2期20卷 103-121页

作者： Soliman, Mostafa I. Al-Junaid, Abdulmajid F. South Valley Univ Aswan Fac Engn Elect Engn Dept Comp & Syst Sect Aswan 81542 Egypt South Valley Univ Fac Engn Elect Engn Dept Comp & Syst Sect Assiut 71515 Egypt

Technological advances in IC manufacturing provide us with the capability to integrate more and more functionality into a single chip. Today's modern processors have nearly one billion transistors on a single chip. With the increasing complexity of today's system, the designs have to be modeled at a high-level of abstraction before partitioning into hardware and software components for final implementation. This paper explains in detail the implementation and performance evaluation of a matrix processor called Mat Core with SystemC (system level modeling language). Mat-Core is a research processor aiming at exploiting the increasingly number of transistors per IC to improve the performance of a wide range of applications. It extends a general-purpose scalar processor with a matrix unit. To hide memory latency, the extended matrix unit is decoupled into two components: address generation and data computation, which communicate through data queues. Like vector architectures, the data computation unit is organized in parallel lanes. However, on parallel lanes, Mat-Core can execute matrix-scalar, matrix-vector, and matrix-matrix instructions in addition to vector-scalar and vector-vector instructions. For controlling the execution of vector/matrix instructions on the matrix core, this paper extends the well known scoreboard technique. Furthermore, the performance of Mat-Core is evaluated on vector and matrix kernels. Our results show that the performance of four lanes Mat-Core with matrix registers of size 4 x 4 or 16 elements each, queues size of 10, start up time of 6 clock cycles, and memory latency of 10 clock cycles is about 0.94, 1.3, 2.3, 1.6, 2.3, and 5.5 FLOPs per clock cycle;achieved on scalar vector multiplication, SAXPY, Givens, rank-1 update, vector-matrix multiplication, and matrix-matrix multiplication, respectively.

关键词： high performance computing multi-level ISA scoreboarding SystemC implementation vector/matrix processing performance evaluation

来源：评论

学校读者我要写书评

暂无评论

FPGA Implementation and Evaluation of a Simple Processor for Multi-scalar/vector/matrix Instructions 2

FPGA Implementation and Evaluation of a Simple Processor for...

引用

2nd International Conference on Engineering and Technology (ICET)

作者： Soliman, Mostafa I. Elsayed, Elsayed A. Taibah Univ Community Coll Comp Sci & Informat Dept Al Madinah Al Munawwarah Saudi Arabia Aswan Univ Fac Engn Dept Elect Engn Comp & Syst Sect Aswan 81542 Egypt

ISBN: (纸本)9781479958078

On FPGA, this paper presents the implementation of a simple processor architecture for accelerating data-parallel applications. Our proposed processor called SuperSMP, which can execute multi-scalar, vector, and matrix instructions on parallel execution datapaths. 4x32-bit instructions are fetched from instruction cache. The fetched instructions are decoded and their dependencies are checked. Up to four independent scalar instructions can be issued in-order to the parallel execution units. However, vector/matrix instructions iterate the issuing of four vector/matrix operations without checking. On four parallel execution units, SuperSMP can perform addition, subtraction, multiplication, division, and shifting on scalar/vector/matrix data. 4x32-bit contiguous vector/matrix elements can be loaded/stored per clock cycle from/to L2 cache to/from matrix register file. Finally, up to 4x32-bit results or loaded data can be written into scalar/matrix register files. The FPGA implementation of our proposed SuperSMP requires 14,032 slices on Xilinx Virtex-5, XC5VLX110-3FF1153. The number of LUT flip-flop pairs is 49,398, where 17,166, 10,267, and 21,965, are the numbers of unused flip-flop, unused LUT, and fully used LUT flip-flop pairs, respectively. The complexity of SuperSMP is about 3.5 times of the baseline scalar processor. However, the performance of SuperSMP ranges from 4.3 to 18.2 times higher than the baseline scalar processor.

关键词： FPGA data-parallel applications vector/matrix processing performance evaluation

来源：评论

学校读者我要写书评

暂无评论

Mat-core: A matrix core extension for general-purpose processors

Mat-core: A matrix core extension for general-purpose proces...

引用

International Conference on Computer Engineering and Systems (ICCES 07)

作者： Soliman, Mostafa I. S Valley Univ Fac Engn Dept Elect Engn Comp & Control Sect Aswan Egypt

ISBN: (纸本)9781424413652

This paper proposes new processor architecture to exploit the increasingly number of transistors per integrated circuit and improve the performance of data parallel applications on general-purpose processors. The proposed processor (called Mat-Core) is based on the use of multi-level ISA to explicitly communicate data parallelism to processor in a compact way cornp,plex hardware or the instead of the dynamic extraction using corn static extraction using sophisticated ier techniques. Since the fundamental data structures for data parallel applications are scalar, vector, and matrix data, Mat-Core extends a scalar core (for executing scalar instructions) with a matrix unit (for executing vector/matrix instructions). Like vector microarchitectures, the extended matrix unit is organized in parallel lanes;each lane contains a pipeline of each functi .. I unit and a slice of the register file. However, the Mat-Core processor can effectively process not only vector but also matrix data on the parallel lanes. The increasingly budget of transistors can be exploited to scale the Mat-core processor by providing more cores in a physical pacU- ge. On a multi-core processor, performance would be improved by parallel processing threads of codes using multi-threading techniques. Index Ternis - data parallel applications, high-performapce computing, parallel architectures, multi-core computation, vector/matrix *** - This paper proposes new processor architecture to exploit the increasingly number of transistors per integrated circuit and improve the performance of data parallel applications on general-purpose processors. The proposed processor (called Mat-Core) is based on the use of multi-level ISA to explicitly communicate data parallelism to processor in a compact way cornp,plex hardware or the instead of the dynamic extraction using corn static extraction using sophisticated ier techniques. Since the fundamental data structures for data parallel applications are

关键词： data parallel applications high-performance computing parallel architectures multi-core computation vector/matrix processing

来源：评论

学校读者我要写书评

暂无评论

OUT-OF-ORDER matrix PROCESSOR: IMPLEMENTATION AND PERFORMANCE EVALUATION

OUT-OF-ORDER MATRIX PROCESSOR: IMPLEMENTATION AND PERFORMANC...

引用

2nd International Conference on Advanced Computer Theory and Engineering (ICACTE 2009)

作者： Soliman, Mostafa I. Al-Junaid, Abdulmajid F. S Valley Univ Comp & Syst Sect Dept Elect Engn Aswan Fac Engn Qena Egypt

ISBN: (纸本)9780791802977

Mat-Core is a research processor aiming at exploiting the increasingly number of transistors per IC to improve the performance of a wide range of applications. It extends a general-purpose scalar processor with a matrix unit for processing vector/matrix data, where scalar and vector/matrix instructions are executed out-of-order. To hid memory latency, the extended matrix unit is decoupled into two components: address generation and data computation, which communicate through data queues and executed also out-of-order. Like vector architectures, the data computation unit is organized in parallel lanes. However, on parallel lanes, Mat-Core can execute scalar-matrix, vector-matrix, and matrix-matrix instructions in addition to scalar-vector and vector-vector instructions. By extending the well known scoreboard algorithm, these instructions are executed out-of-order on parallel pipelines. This paper describes the SystemC (system level modeling language) implementation of Mat-Core and evaluates its performance on vector and matrix kernels. On four parallel lanes and matrix registers of size 4x8 or 32 elements each, the performance of Mat-Core with queues size of 10, start up time of 6 clock cycles, and memory latency of 10 clock cycles, is about 1.4, 2.1, 4.2, 2.6, 4.2, and 6.4 FLOPs per clock cycle;achieved on scalar-vector multiplication, SAXPY, Givens, rank-1 update, vector-matrix multiplication, and matrix-matrix multiplication, respectively.

关键词： vector/matrix processing out-of-order execution decoupled architectures SystemC implementation performance evaluation

来源：评论

学校读者我要写书评

暂无评论

FPGA Implementation and Performance Evaluation of a Simultaneous Multithreaded matrix Processor 9

FPGA Implementation and Performance Evaluation of a Simultan...

引用

9th International Conference on Computer Engineering & Systems (ICCES)

作者： Soliman, Mostafa I. Elsayed, Elsayed A. Aswan Univ Dept Elect Engn Fac Engn Comp & Syst Sect Aswan 81542 Egypt

ISBN: (纸本)9781479965946

This paper proposes a simultaneous multithreaded matrix processor called SMMP to improve the performance of data-parallel applications by exploiting ILP, DLP, and TLP. In SMMP, the well-known 5-stage pipeline (baseline scalar processor) is extended to execute multi-scalar/vector/matrix instructions on unified parallel execution datapaths. SMMP can issue four scalar instructions from two threads each cycle or four vector/matrix operations from one thread, where the execution of vector/matrix instructions in threads is done in round-robin fashion. Moreover, this paper presents the implementation of our proposed SMMP using VHDL targeting FPGA Virtex-6. In addition, the performance of SMMP is evaluated on some kernels from the basic linear algebra subprograms (BLAS). Our results show that, the hardware complexity of SMMP is 5.68 times higher than the baseline scalar processor. However, speedups of 4.9, 6.09, 6.98, 8.2, 8.25, 8.72, 9.36, 11.84, and 21.57 are achieved on BLAS kernels of applying Givens rotation, scalar times vector plus another, vector addition, vector scaling, setting up Givens rotation, dot-product, matrix-vector multiplication, Euclidean length, and matrix-matrix multiplications, respectively. In conclusion, the average speedup over the baseline is 9.55 and the average speedup over complexity is 1.68.

关键词： data-parallel applications simultaneous multithreading vector/matrix processing performance evaluation FPGA/VHDL implementation

来源：评论

学校读者我要写书评

暂无评论

SystemC Implementation of Mat-Core: A matrix Core Extension for General-Purpose Processors

SystemC Implementation of Mat-Core: A Matrix Core Extension ...

引用

4th IEEE International Conference on Design and Technology of Integrated Systems in Nanoscale Era

作者： Soliman, Mostafa I. Al-Junaid, Abdulmajid F. S Valley Univ Aswan Fac Engn Dept Elect Engn Comp & Syst Sect Kena Egypt Assiunt Univ Fac Engn Dept Elect Engn Comp & Syst Sect Assiut Egypt

ISBN: (纸本)9781424443208

关键词： high performance computing multi-level ISA scoreboarding SystemC implementation vector/matrix processing

来源：评论

学校读者我要写书评

暂无评论

DCT Implementation and Performance Evaluation on a Scalable matrix Processor

DCT Implementation and Performance Evaluation on a Scalable ...

引用

6th International Conference on Computer Engineering and Systems (ICCES)

作者： Soliman, Mostafa I. Al-Junaid, Abdulmajid F. South Valley Univ Comp & Syst Sect Elect Engn Dep Aswan Fac Engn Aswan 81542 Egypt

ISBN: (纸本)9781424470426

Discrete cosine transform (DCT) is one of the major operations in various image/video compression standards. This paper implements DCT and its inverse (IDCT) on our proposed Mat-Core processor using scalar/vector/matrix instruction sets. Mat-Core extends a general-purpose scalar processor with a matrix unit for processing vector/matrix data. The extended matrix unit is decoupled into two components to hide memory latency: address generation and data computation, which communicate through data queues. The data computation unit is organized in parallel lanes, which can execute scalar-vector, vector-vector, scalar-matrix, vector-matrix, and matrix-matrix instructions. To show the scalability of Mat-Core architecture, the performance of DCT and IDCT are evaluated on Mat-Core with different number of parallel lanes (one, four, and eight lanes). A cycle accurate model of Mat-Core processor is implemented using SystemC (system level modeling language). Our results show performances of 1.5, 5, 6.4 and 14.4 FLOPs/cycle on Mat-Core with single lane and 8-element vector registers, four lanes and 4x4 matrix registers, four lanes and 8x4 matrix registers, and eight lanes and 8x8 matrix registers, respectively. The maximum performance of the Mat-Core processor on DCT and IDCT represents 90% of the ideal value. Moreover, increasing the number of parallel lanes from one to four and then to eight results in speeding up the execution of DCT and IDCT by factors of 4.2 and 9.5, respectively, which indicates the scalability of Mat-Core architecture.

关键词： DCT/IDCT high performance computing performance evaluation scalable architecture SystemC implementation vector/matrix processing

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：