Multiple input multiple output (MIMO) technology is anticipated to play a key role in future wirelesscommunications systems. However, one of the main challenges of MIMO technology is the high complexity of the signal...
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ISBN:
(纸本)9781538663653
Multiple input multiple output (MIMO) technology is anticipated to play a key role in future wirelesscommunications systems. However, one of the main challenges of MIMO technology is the high complexity of the signal detection, which results in a high power consumption at the MIMO receiver. In this paper, we present the hardware implementation of a K-best detector based on a single-stage architecture, targeted at low-rate and low-power applications. To achieve a low complexity, we optimise the sorting stage of the detector by systematically eliminating redundant comparators. Furthermore, the sorter incorporates different merge algorithms at selected stages in order to reduce the total comparator count. For a 64-QAM 4 x 4 MIMO system, the detector achieves a power consumption of 34 mW using the STMicroelectronics 65 nm CMOS library, which compares favourably with similar works from the literature.
QR decomposition is extensively adopted in multiple-input-multiple-output orthogonal frequency-division multiplexing wirelesscommunication systems, and is one of the performance bottlenecks in lots of high-performanc...
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QR decomposition is extensively adopted in multiple-input-multiple-output orthogonal frequency-division multiplexing wirelesscommunication systems, and is one of the performance bottlenecks in lots of high-performance wireless communication algorithms. To implement low processing latency QR decomposition with hardware, the authors propose a novel iterative look-ahead modified Gram-Schmidt (ILMGS) algorithm based on the traditional modified Gram-Schmidt (MGS) algorithm. They also design the corresponding triangular systolic array (TSA) architecture with the proposed ILMGS algorithm, which only needs n time slots for a n x n real matrix. For reducing the hardware overhead, they modify the TSA architecture into an iterative architecture. They also design a modified iterative architecture to further reduce the hardware overhead. The implementation results show that the normalised processing latency of the modified iterative architecture based on the proposed ILMGS algorithm is 1.36 times lower than the one based on the MGS algorithm. To the best of the authors' knowledge, the designed architecture achieves the superior latency performance than the existing works.
Future mobile communication systems have to be flexible while adapting to environmental conditions and user demands. These systems also have to be energy-efficient as they are used in battery-operated terminals. We ex...
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Future mobile communication systems have to be flexible while adapting to environmental conditions and user demands. These systems also have to be energy-efficient as they are used in battery-operated terminals. We expect that heterogeneous reconfigurable hardware can overcome the contradicting requirements in flexibility, energy-efficiency and performance. A coarse-grain reconfigurable processor, called MONTIUM, is presented. An overview of a wireless LAN communication system, HiperLAN/2, and a Bluetooth communication system will be given. Possible implementations of these systems in heterogeneous reconfigurable hardware are discussed. Performance figures of the implemented HiperLAN/2 baseband processing in the MoNTium architecture are presented. The required performance can be obtained at low clock frequencies with small configuration overhead. The flexibility of the MONTIUM is shown, as the baseband processing of both HiperLAN/2 and Bluetooth is implemented on the same architecture.
This paper discusses the implementation of multi-standard communication systems in dynamically reconfigurable heterogeneous hardware. An overview of a wireless LAN communication system, namely HiperLAN/2, and a Blueto...
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ISBN:
(纸本)193241505X
This paper discusses the implementation of multi-standard communication systems in dynamically reconfigurable heterogeneous hardware. An overview of a wireless LAN communication system, namely HiperLAN/2, and a Bluetooth communication system will be given. Possible implementations of these systems in a reconfigurable architecture are discussed. Suggestions for future activities in the Adaptive wireless Networking project are also given.
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