A new configuration for delay cells used in voltage controlled oscillators is presented. A jitter comparison between the source-coupled differential delay cell and the proposed CMOS inverter based delay cell is given....
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A new configuration for delay cells used in voltage controlled oscillators is presented. A jitter comparison between the source-coupled differential delay cell and the proposed CMOS inverter based delay cell is given. A new method to optimize loop parameters based on low-jitter in PLL is also introduced. A low-jitter 1.25GHz Serdes is implemented in a 0.35μm standard 2P3M CMOS process. The result shows that the RJ （random jitter） RMS of 1.25GHz data rate series output is 2. 3ps （0. 0015UI） and RJ （1 sigma） is 0. 0035UI. A phase noise measurement shows - 120dBc/Hz@100kHz at 1111100000 clock-pattern data out.
We present a new hybrid digital pulse-width modulator （DPWM） for digital DC-DC converters that employs a ring-oscillator/counter structure. Based on a temperature/process compensation technique and a novel digital c...
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We present a new hybrid digital pulse-width modulator （DPWM） for digital DC-DC converters that employs a ring-oscillator/counter structure. Based on a temperature/process compensation technique and a novel digital controller, the proposed DPWM can not only offer temperature/process-independent pulse widths, but also operate at a much higher clock frequency than the existing delay-line/counter DPWM structure. Post-simulation results show that with our DPWM, the system clock frequency reaches 156.9MHz while the worst variation,in a temperature range of 0 to 100℃under all process corners,is only± 9.4%.
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