A CMOS folding and interpolating analog-to-digital converter (ADC) for embedded application is *** circuit is fully compatible with standard digital CMOS technology.A modified folding block implemented without resisto...
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A CMOS folding and interpolating analog-to-digital converter (ADC) for embedded application is *** circuit is fully compatible with standard digital CMOS technology.A modified folding block implemented without resistor contributes to a small chip *** the input stage,offset averaging reduces the input capacitance and the distributed track-and-hold circuits are proposed to improve signal-to-noise-plus-distortion *** 200Ms/s 8bit ADC with 177mW total power consumption at 3.3V power supply is realized in standard digital 0.18μm 3.3V CMOS technology.
A 1.8-V 64-kb four-way set-associative CMOS cache memory implemented by 0.18μm/1.8V 1P6M logic CMOS technology for a super performance 32-b RISC microprocessor is *** comparison,a conventional parallel access cache w...
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A 1.8-V 64-kb four-way set-associative CMOS cache memory implemented by 0.18μm/1.8V 1P6M logic CMOS technology for a super performance 32-b RISC microprocessor is *** comparison,a conventional parallel access cache with the same storage and organization is also designed and simulated using the same *** results indicate that by using sequential access,power reduction of 26% on a cache hit and 35% on a cache miss is ***-speed approaches including modified current-mode sense amplifier and split dynamic tag comparators are adopted to achieve fast data *** results indicate that a typical clock to data access of 2.7ns is achieved...
A 1.8V 8b 125Msample/s pipelined A/D converter is *** efficiency is optimized by size scaling down scheme using low power single stage cascode amplifier with a gain boosted *** clock tree and local generators are empl...
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A 1.8V 8b 125Msample/s pipelined A/D converter is *** efficiency is optimized by size scaling down scheme using low power single stage cascode amplifier with a gain boosted *** clock tree and local generators are employed to avoid loss and overlap of clock *** ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 49.5dB(7.9ENOB) for an input of 62MHz at full speed of 125MHz,consuming only *** is implemented in 0.18μm CMOS technology with a core area of 0.45mm 2.
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