This paper presents a new quasi-static single-phase energy recovery logic （QSSERL）, which unlike any other existing adiabatic logic family,uses a single sinusoidal supply-clock without additional timing control volt...
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This paper presents a new quasi-static single-phase energy recovery logic （QSSERL）, which unlike any other existing adiabatic logic family,uses a single sinusoidal supply-clock without additional timing control volta- ges. This not only ensures lower energy dissipation, but also simplifies the clock design, which would be otherwise more complicated due to the signal synchronization requirement. It is demonstrated that QSSERL circuits operate as fast as conventional two-phase energy recovery logic counterparts. Simulation with an 8bit logarithmic look- ahead adder （LLA） using static CMOS,clocked CMOS adiabatic logic （CAL,an existing typical single-phase ener- gy recovery logic）,and QSSERL,under 128 randomly generated input vectors,shows that the power consumption of the QSSERL adder is only 45% of that of the conventional static CMOS counterpart at 10MHz, and the QS- SERL adder achieves better energy efficiency than CAL when the input frequency finput is larger than 2MHz.
A stereo 1.5bit delta-sigma digital-analog converter （△∑ DAC） integrated with a filterless class D power amplifier is introduced. It consumes no static power, and its maximum output power is 436mW with an 8Ω load...
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A stereo 1.5bit delta-sigma digital-analog converter （△∑ DAC） integrated with a filterless class D power amplifier is introduced. It consumes no static power, and its maximum output power is 436mW with an 8Ω load. Its output dynamic range exceeds 100dB. The circuit is implemented with a TSMC 0. 18μm process. The die area is 0. 28mme. The supply voltage is 1. gV for the digital part and 3.3V for class D.
提出了一种全新的射频识别(RFID)数字接收机的实现方案。针对RFID系统实时性的要求,该设计采用简化的相关算法取代数字锁相环结构,快速准确地捕获频率范围在31.2kHz-780.8kHz内的突发信号,并实现接收数据解码。与采用过零检测方案的数字接收机相比,本设计具有更强的抗干扰能力。该数字接收机在Altera Stratix II EP2S60上验证通过,取得了良好的性能。
This paper presents a three-stage CMOS operational amplifier （opamp） that combines accuracy with stability for a wide range of capacitive loads. A so-called quenching capacitor is added to a multipath nested Miller ...
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This paper presents a three-stage CMOS operational amplifier （opamp） that combines accuracy with stability for a wide range of capacitive loads. A so-called quenching capacitor is added to a multipath nested Miller compensation （MNMC） topology to obtain stability for a wide range of capacitive loads. Theoretical analysis and mathematical formulas are provided to prove the improvement in stability. A prototype of this frequency compen- sation scheme is implemented in a 0.7μm CMOS process. Measurement′s show that the amplifier can drive capaci- tive loads ranging from 100pF to 100/μF with a gain of 90dB and a minimum phase margin of 26°. The amplifier has a unity-gain bandwidth of 1MHz for a 100pF capacitive load. It employs a quenching capacitance of 18pF.
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