A single-chip DVB-C quadrature amplitude modulation（QAM） demodulator is proposed,which integrates a 3.3V 10bit 40MSPS analog-to-digital converter and a forward error correction decoder. The demodulator chip can supp...
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A single-chip DVB-C quadrature amplitude modulation（QAM） demodulator is proposed,which integrates a 3.3V 10bit 40MSPS analog-to-digital converter and a forward error correction decoder. The demodulator chip can support 4-256 QAM with variable bit rate up to 80Mbps. It features a wide carrier offset acquisition range,optimal demodulation algorithm,and small circuit area. The chip is implemented in SMIC 0.25μm 1P5M mixed-signal CMOS technology with a die size of 3.5mm×3. 5mm. The maximum power consumption is 447mW.
This paper describes a 3.0V, 10b,40Msample/s analog-to-digital converter （ADC） fabricated in a 0.25μm CMOS technology. Through the sharing an amplifier between two successive pipeline stages, the converter is reali...
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This paper describes a 3.0V, 10b,40Msample/s analog-to-digital converter （ADC） fabricated in a 0.25μm CMOS technology. Through the sharing an amplifier between two successive pipeline stages, the converter is realized using just four amplifiers with a separate sample-and-hold block. It employs two key techniques： a high bandwidth low-power gain-boosting telescopic amplifiers technique and a low power low offset dynamic comparators *** ADC achieves a 8.1 effective number of bits,a maximum differential nonlinearity of a 0.85 least significant bit（LSB）, and maximum integral nonlinearity of 2.2LSB for a 0.5MHz input at full sampling rate. It occupies 1.24mm^2 ,which also includes a bandgap and a voltage reference circuit and dissipates only 59mW.
文章解决了将“变方向隐式方法的三维时域有限差分法”(3D AD I-FDTD)应用于高速芯片内互连线的电磁场计算中很多关键问题,包括源的产生方案及其数值结构,具体边界吸收条件的差分格式。特别是针对芯片互连线中的多层介质、多导体线的结...
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文章解决了将“变方向隐式方法的三维时域有限差分法”(3D AD I-FDTD)应用于高速芯片内互连线的电磁场计算中很多关键问题,包括源的产生方案及其数值结构,具体边界吸收条件的差分格式。特别是针对芯片互连线中的多层介质、多导体线的结构,提出了稀疏的矩阵模型和可变网格的划分。数值实验表明,对原有AD I-FDTD方法所做的这些改进,能够在保证适当精度的情况下提高计算速度。
This paper presents a fully integrated 4 8GHz VCO with an invention——symmetrical noise filter *** VCO,with relatively low phase noise and large tuning range of 716MHz,is fabricated with the 0 25μm SMIC CMOS *** o...
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This paper presents a fully integrated 4 8GHz VCO with an invention——symmetrical noise filter *** VCO,with relatively low phase noise and large tuning range of 716MHz,is fabricated with the 0 25μm SMIC CMOS *** oscillator consumes 6mA from 2 5V *** conventional VCO is also designed and simulated without symmetrical noise filter on the same process,which also consumes 6mA current and is with the same *** result describes that the first VCO’ phase noise is 6dBc/Hz better than the latter’s at the same offset frequency from 4 *** phase noise at 1MHz away from the carrier in this 4 8GHz VCO with symmetrical noise filter is -123 66dBc/*** design is suitable for the usage in a phase locked loop and other consumer *** is amenable for future technologies and allows easy porting to different CMOS manufacturing process.
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