A novel divider based on dual-bit algorithm and its VLSI implementation are *** with the divider of MIPS microprocessor,it decreases the average executing cycles by 52.5% while its maximum delay is almost the same and...
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A novel divider based on dual-bit algorithm and its VLSI implementation are *** with the divider of MIPS microprocessor,it decreases the average executing cycles by 52.5% while its maximum delay is almost the same and its transistor count increases by 60%.Furthermore,the simulation result indicates that the power consumption decreases to 11.3% with the same processing ability.
A CMOS folding and interpolating analog-to-digital converter (ADC) for embedded application is *** circuit is fully compatible with standard digital CMOS technology.A modified folding block implemented without resisto...
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A CMOS folding and interpolating analog-to-digital converter (ADC) for embedded application is *** circuit is fully compatible with standard digital CMOS technology.A modified folding block implemented without resistor contributes to a small chip *** the input stage,offset averaging reduces the input capacitance and the distributed track-and-hold circuits are proposed to improve signal-to-noise-plus-distortion *** 200Ms/s 8bit ADC with 177mW total power consumption at 3.3V power supply is realized in standard digital 0.18μm 3.3V CMOS technology.
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