This paper presents the design considerations and implementation of an area-efficient interpolator suitable for a delta-sigma D/A converter. In an effort to reduce the area and design complexity, a method for designin...
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This paper presents the design considerations and implementation of an area-efficient interpolator suitable for a delta-sigma D/A converter. In an effort to reduce the area and design complexity, a method for designing an FIR filter as a tapped cascaded interconnection of identical subfilters is modified. The proposed subfilter structure further minimizes the arithmetic number. Experimental results show that the proposed interpolator achieves the design specification,exhibiting high performance and hardware efficiency,and also has good noise rejection capability. The interpolation filter can be applied to a delta-sigma DAC and is fully functional.
A 16bit sigma-delta audio analog-to-digital converter is *** consists of an analog modulator and a digital decimator.A standard 2-order single-loop architecture is employed in the *** stabilization is applied to the f...
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A 16bit sigma-delta audio analog-to-digital converter is *** consists of an analog modulator and a digital decimator.A standard 2-order single-loop architecture is employed in the *** stabilization is applied to the first integrator to eliminate the 1/f noise.A low-power,area-efficient decimator is used,which includes a poly-phase comb-filter and a *** converter achieves a 92dB dynamic range over the 96kHz audio *** single chip occupies 2.68mm2 in a 0.18μm six-metal CMOS process and dissipates only 15.5mW power.
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