A novel charge exchanging compensation （CEC） technique is proposed for a wideband sample-and-hold （S/H） circuit applied in an IF sampling ADC. The CEC technique compensates the sampling bandwidth by eliminating th...
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A novel charge exchanging compensation （CEC） technique is proposed for a wideband sample-and-hold （S/H） circuit applied in an IF sampling ADC. The CEC technique compensates the sampling bandwidth by eliminating the impact from finite on-resistance of the sampling switch, and avoids increasing clock feedthrough and charge injection. Meanwhile, a low power two stage OTA with a class AB output stage is designed to provide the S/H a 3Vp-p input range under 1.8V power. The S/H achieves a 94dB spurious-free dynamic range for a 200MHz input signal at a 100Ms/s sample rate and consumes only 26mW with a 5.5pF load.
A fractional-N frequency synthesizer for 433/868MHz SRD applications is implemented in a 0.3μm CMOS process. A wide-band VCO and an AFC are used to cover the desired bands. A 3bit third order sigma-delta modulator is...
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A fractional-N frequency synthesizer for 433/868MHz SRD applications is implemented in a 0.3μm CMOS process. A wide-band VCO and an AFC are used to cover the desired bands. A 3bit third order sigma-delta modulator is adopted to reduce the out-band phase noise. The measurements show a VCO tuning range from 1.31 to 1.88GHz with AFC working correctly,an out-band phase noise of -139dBc/Hz at 3MHz offset frequency, and a fractional spur of less than - 60dBc. The chip area is 1.5mm × 1.2mm and the total current dissipation including LO buffers is 19mA from a single 3.0V supply voltage.
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