A 1.8V 8b 125Msample/s pipelined A/D converter is *** efficiency is optimized by size scaling down scheme using low power single stage cascode amplifier with a gain boosted *** clock tree and local generators are empl...
详细信息
A 1.8V 8b 125Msample/s pipelined A/D converter is *** efficiency is optimized by size scaling down scheme using low power single stage cascode amplifier with a gain boosted *** clock tree and local generators are employed to avoid loss and overlap of clock *** ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 49.5dB(7.9ENOB) for an input of 62MHz at full speed of 125MHz,consuming only *** is implemented in 0.18μm CMOS technology with a core area of 0.45mm 2.
暂无评论