A new,low-cost RFid tag analog front-end compatible with ISO 14443A and ISO 14443B is presented. By substituting conventional multi-circle antenna with single-circle antenna, the package cost of the tag is greatly red...
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A new,low-cost RFid tag analog front-end compatible with ISO 14443A and ISO 14443B is presented. By substituting conventional multi-circle antenna with single-circle antenna, the package cost of the tag is greatly reduced. Based on this exasperate antenna performance,a new rectifier with high power conversion efficiency and low turn-on voltage is presented. The circuit is implemented in an SMIC 0.18μm EEPROM process. Measurement results show that with a 120kΩ load,the power conversion efficiency reaches as high as 36%. For a sinusoidal wave with magnitude of 0. 5V, the output DC voltage reaches IV,which is high enough for RFid tags. The read distance is as far as 22cm.
A quadrature mixer with a shared transconductor stage is analyzed,including voltage conversion gain, linearity, noise figure, and image rejection. The analysis indicates it has better performance than a conventional G...
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A quadrature mixer with a shared transconductor stage is analyzed,including voltage conversion gain, linearity, noise figure, and image rejection. The analysis indicates it has better performance than a conventional Gilbert mixer pair in commutating mode. A quadrature down-conversion mixer based on this topology is designed and optimized for an ultra high frequency RFid reader. Operating in the 915MHz ISM band, the presented quadrature mixer measures a conversion gain of 12.5dB,an IIP3 of 10dBm, an IIP2 of 58dBm, and an SSB noise figure of 17.6riB. The chip was fabricated in a 0. 18μm 1P6M RF CMOS process and consumes only 3mA of current from a 1.8V power supply.
A novel Fudan programmable logic chip （FDP） was designed and implemented with a SMIC 0. 18μm CMOS logic process. The new 3-LUT based logic cell circuit increases logic density about 11% compared with a traditional ...
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A novel Fudan programmable logic chip （FDP） was designed and implemented with a SMIC 0. 18μm CMOS logic process. The new 3-LUT based logic cell circuit increases logic density about 11% compared with a traditional 4-input LUT. The unique hierarchy routing fabrics and effective switch box optimize the routing wire segments and make it possible for different lengths to connect directly. The FDP contains 1,600 programmable logic cells, 160 programmable I/O, and 16kbit dual port block RAM. Its die size is 6. 104mm× 6. 620mm, with the package of QFP208. The hardware and software cooperation tests indicate that FDP chip works correctly and efficiently.
A direct conversion receiver with optimized tolerance to local carrier interference is designed and implemented in a 0.18μm 1P6M mixed-signal CMOS process for a 900MHz RFid reader transceiver. A baseband amplifier wi...
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A direct conversion receiver with optimized tolerance to local carrier interference is designed and implemented in a 0.18μm 1P6M mixed-signal CMOS process for a 900MHz RFid reader transceiver. A baseband amplifier with series feedback topology is proposed to achieve passive mixer buffering,baseband DC cancellation,and signal amplification simultaneously. The receiver has a measured input ldB compression point of - 4dBm and a sensitivity of - 70dBm when 10dB SNR for digital demodulation is required. The receiver is integrated in a reader transceiver chip and consumes 90mA from a 1.8V supply.
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