A 1.9GHz down-conversion CMOS mixer with a novel folded Gilbert cell,intended for use in GSM1900 （PCS1900） low-IF receivers,is fabricated in a RF 0.18μm CMOS process. The prototype demonstrates good performance at ...
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A 1.9GHz down-conversion CMOS mixer with a novel folded Gilbert cell,intended for use in GSM1900 （PCS1900） low-IF receivers,is fabricated in a RF 0.18μm CMOS process. The prototype demonstrates good performance at an intermediate frequency of 100kHz. It achieves a conversion gain of 6dB, SSB noise figure of 18. 5dB （1MHz IF） ,and IIP3 11.5dBm while consuming a 7mA current from a 3.3V power supply.
A stereo 1.5bit delta-sigma digital-analog converter （△∑ DAC） integrated with a filterless class D power amplifier is introduced. It consumes no static power, and its maximum output power is 436mW with an 8Ω load...
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A stereo 1.5bit delta-sigma digital-analog converter （△∑ DAC） integrated with a filterless class D power amplifier is introduced. It consumes no static power, and its maximum output power is 436mW with an 8Ω load. Its output dynamic range exceeds 100dB. The circuit is implemented with a TSMC 0. 18μm process. The die area is 0. 28mme. The supply voltage is 1. gV for the digital part and 3.3V for class D.
This paper presents a new quasi-static single-phase energy recovery logic （QSSERL）, which unlike any other existing adiabatic logic family,uses a single sinusoidal supply-clock without additional timing control volt...
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This paper presents a new quasi-static single-phase energy recovery logic （QSSERL）, which unlike any other existing adiabatic logic family,uses a single sinusoidal supply-clock without additional timing control volta- ges. This not only ensures lower energy dissipation, but also simplifies the clock design, which would be otherwise more complicated due to the signal synchronization requirement. It is demonstrated that QSSERL circuits operate as fast as conventional two-phase energy recovery logic counterparts. Simulation with an 8bit logarithmic look- ahead adder （LLA） using static CMOS,clocked CMOS adiabatic logic （CAL,an existing typical single-phase ener- gy recovery logic）,and QSSERL,under 128 randomly generated input vectors,shows that the power consumption of the QSSERL adder is only 45% of that of the conventional static CMOS counterpart at 10MHz, and the QS- SERL adder achieves better energy efficiency than CAL when the input frequency finput is larger than 2MHz.
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