By measurement,we investigate the characteristics and location of gate oxide damage induced by snapback stress. The damage incurred during stress causes device degradation that follows an approximate power law with st...
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By measurement,we investigate the characteristics and location of gate oxide damage induced by snapback stress. The damage incurred during stress causes device degradation that follows an approximate power law with stress time. Oxide traps generated by stress will cause the increase of stress-induced leakage current and the decrease of Qbd （charge to breakdown）,and it may also cause the degradation of off-state drain leakage current. Stress-induced gate oxide damage is located not only in the drain side but also in the source side. The tertiary electrons generated by hot holes move toward Si-SiO2 interface under the electrical field toward the substrate,which explains the source side gate oxide damage.
Based on the physical characteristics of SiGe material,a new three-dimensional （3D） CMOS IC structure is proposed,in which the first device layer is made of Si material for nMOS devices and the second device layer i...
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Based on the physical characteristics of SiGe material,a new three-dimensional （3D） CMOS IC structure is proposed,in which the first device layer is made of Si material for nMOS devices and the second device layer is made of Six Ge1- x material for pMOS. The intrinsic performance of ICs with the new structure is then limited by Si *** electrical characteristics of a Si-SiGe 3D CMOS device and inverter are all simulated and analyzed by MEDICI. The simulation results indicate that the Si-SiGe 3D CMOS ICs are faster than the Si-Si 3D CMOS ICs. The delay time of the 3D Si-SiGe CMOS inverter is 2-3ps,which is shorter than that of the 3D Si-Si CMOS inverter.
We investigate the negative bias temperature instability （NBTI） of 90nm pMOSFETs under various temperatures and stress gate voltages （Vg）. We also study models of the time （t） ,temperature （T） ,and stress Vg d...
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We investigate the negative bias temperature instability （NBTI） of 90nm pMOSFETs under various temperatures and stress gate voltages （Vg）. We also study models of the time （t） ,temperature （T） ,and stress Vg dependence of 90nm pMOSFETs NBTI degradation. The time model and temperature model are similar to previ- ous studies, with small difference in the key coefficients. A power-law model is found to hold for Vg, which is different from the conventional exponential Vg model. The new model is more predictive than the exponential model when taking lower stress Vg into account.
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