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Asia-Pacific Conference on Software Engineering

作者： He Jifeng C.A.R. Hoare International Institute for Software Technology United Nations University Macau Macao China Computing Laboratory Programming Research Group Oxford University Oxford UK

A theory of programming starts with a complete Boolean algebra of specifications, and defines healthiness conditions which exclude infeasibility of implementation. These are expressed as algebraic laws useful for transformation and optimisation of designs. programming notations and languages must be restricted to those preserving all the healthiness conditions. We have explored a wide range of programming paradigms, including nondeterministic, sequential, parallel, logical and probabilistic. In all cases, we have found a single healthiness condition, formalised by constructions due to Karoubi and to Kleisli. The uniformity maintains for all paradigms a single notion of correctness throughout the chain that leads from specification through designs to programs that are proved to meet the original specification.

关键词： Design optimization Laboratories Boolean algebra Logic programming Parallel programming Maintenance Specification languages

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Implementation lessons of performance prediction tool for parallel conservative simulation 6

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6th International European Conference on Parallel computing, Euro-Par 2000

作者： Lim, Chu-Cheow Low, Yoke-Hean Gan, Boon-Ping Cai, Wentong Intel Corporation SC12-305 2000 Mission College Blvd Santa ClaraCA95052-8119 United States Programming Research Group Oxford University Computing Laboratory University of Oxford OxfordOX1 3QD United Kingdom Gintic Institute of Manufacturing Technology 71 Nanyang Drive Singapore638075 Singapore Center for Advanced Information Systems School of Applied Science Nanyang Technological University Singapore639798 Singapore

ISBN: (纸本)9783540679561

Performance prediction is useful in helping parallel programmers answer questions such as speedup scalability. Performance prediction for parallel simulation requires first working out the performance analyzer algorithms for specific simulation protocols. In order for the prediction results to be close to the results from actual parallel executions, there are further considerations when implementing the analyzer. These include (a) equivalence of code between the sequential program and parallel program, and (b) system effects (e.g. cache miss rates and synchronization overheads in an actual parallel execution). This paper describes our investigations into these issues on a performance analyzer for a conservative, "super-step" (synchronous) simulation protocol. © Springer-Verlag Berlin Heidelberg 2000.

关键词： Forecasting

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PRAM programming: in theory and in practice

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Concurrency and Computation: Practice and Experience 2000年第4期12卷

作者： D. S. Lecomber C. J. Siniolakis K. R. Sujithan Programming Research Group Oxford University Computing Laboratory Oxford OX1 3QD U.K.

That the influence of the PRAM model is ubiquitous in parallel algorithm design is as clear as the fact that it is technologically infeasible for the forseeable future. The current generation of parallel hardware prominently features distributed memory and high-performance interconnection networks—very much the antithesis of the shared memory required for the PRAM model. It has been shown that, in spite of communication costs, for some problems very fast parallel algorithms are available for distributed-memory machines—from embarassingly parallel problems to sorting and numerical analysis. In contrast it is known that for other classes of problem PRAM-style shared-memory simulation on a distributed-memory machine can, in theory, produce solutions of comparable performance to the best possible for such architectures. The Bulk Synchronous Parallel (BSP) model accurately represents most parallel machines—theoretical and actual—in an execution and cost model. We introduce a scalable portable PRAM realization appropriate for BSP computers and a methodology for usage. Our system is fast and built upon the familiar sequential C++ coupled with the new standard BSP library of parallel computation and communication primitives. It is portable to and predictable on a vast number of parallel computers including workstation clusters, a 256-processor Cray T3D, an 8-node IBM SP/2 and a 4-node shared-memory SGI Power Challenge machine. Our approach achieves simplicity of programming over direct-mode BSP programming for reasonable overhead cost. We objectively compare optimized BSP and PRAM algorithms implemented with our C++ PRAM library and provide encouraging experimental results for our new style of programming. Copyright © 2000 John Wiley & Sons, Ltd.

关键词： PRAM latency hiding BSP distributed memory simulation parallel algorithms

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Hardware/software codesign for FPGA-based systems

Hardware/software codesign for FPGA-based systems

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Annual Hawaii International Conference on System Sciences (HICSS)

作者： J.M. Saul Computing Laboratory Programming Research Group Oxford University Oxford UK

A new codesign compiler called Dash (Design Automation for Software and Hardware) provides a co-synthesis and co-simulation environment for mixed FPGA/processor architectures. It compiles a C-like description to a solution containing both processors and custom hardware, and allows the descriptions of FPGA-based processors to be heavily parametrised. The user may add instructions to the processors, and the Dash software architecture allows the user to add facilities for targeting these extra instructions to the compiler. This system is being used to design a number of case studies, and a single-chip codesign of an Internet video game is used to illustrate the design flow.

关键词： Hardware Field programmable gate arrays Software systems Computer architecture Design automation Application software Software tools Acceleration Laboratories Hip

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A framework for model-checking timed CSP

A framework for model-checking timed CSP

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IEE Colloquium on Applicable Modelling, Verification and Analysis Techniques for Real-Time Systems (Ref. No. 1.99/006)

作者： J. Ouaknine Programming Research Group Oxford University Computing Laboratory UK

Timed CSP is a well-known process algebra, built as an extension to Hoare's original CSP, designed to handle concurrency combined with timing considerations. It achieves this over a continuous time domain (the non-negative real numbers), which has the drawback of precluding standard model-checking approaches, as the state-space of any process is naturally a priori (uncountably) infinite. This paper shows how to circumvent this problem by translating and reinterpreting timed CSP processes within a new model of standard CSP. In this discrete model, which draws on previous work by A.W. Roscoe (1.97) and A. Mukkaram (1.93), timing of events is provided by the consistent and regular communication of a special tock event, analogous to the 'tick' of a clock. The various parallel components of a process are therefore required to synchronise on tock, ensuring a uniform rate of passage of time. General results yielding tight bounds on the loss of information inherent to the translation are given.

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Efficient deterministic sorting on the BSP model

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Parallel Processing Letters 1999年第1期9卷 69-79页

作者： Gerbessiotis, Alexandros V. Programming Research Group Computing Laboratory Oxford University Oxford OX1 3QD United Kingdom

We present a new algorithm for deterministic sorting on the Bulk-Synchronous Parallel (BSP) model of computation. We sort n keys using a partitioning scheme that achieves the requirements of efficiency (one-optimality) and insensitivity against initial key distribution. Although we employ sampling to realize efficiency, we give a precise worst-case estimation of the maximum imbalance which might occur. The algorithm is one-optimal for a wide range of the BSP parameters in the sense that its speedup on p processors is asymptotically (1.- o(1.) p.

关键词： Parallel algorithms

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Re-synthesis in technology mapping for heterogeneous FPGAs

Re-synthesis in technology mapping for heterogeneous FPGAs

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IEEE International Conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： M. Inuani J. Saul Programming Research Group Oxford University Computing Laboratory Oxford UK

Field programmable gate arrays containing more than one size of lookup-table occupy a large and growing portion of the market, but technology mapping for these architectures has hardly been considered. New algorithms have been developed for decomposition, covering and restructuring targeted at these architectures. Benchmark results show that the new method produces circuits which are on average 1.% smaller than the best previous approach we know of.

关键词： Field programmable gate arrays Table lookup Cost function Logic circuits Laboratories Programmable logic arrays Consumer electronics Reconfigurable logic Prototypes Integrated circuit interconnections

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PRAM programming: theory vs. practice

PRAM programming: theory vs. practice

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Euromicro Workshop on Parallel and Distributed Processing

作者： A.V. Gerbessiotis D.S. Lecomber C.J. Siniolakis K.R. Sujithan Programming Research Group Computing Laboratory Oxford University Oxford UK

We investigate the practical viability of PRAM programming within the BSP framework. We argue that there is a necessity for PRAM computations in situations where the problem exhibits poor data locality. We introduce a C++ PRAM simulator that is built on top of the {1. BSP Toolset, BSPlib, and provide a succinct PRAM language. Our approach achieves simplicity of programming over direct-mode BSP programming for reasonable overhead cost. We objectively compare optimized BSP algorithms with PRAM algorithms implemented with our library and provide encouraging experimental results for the latter style of programming.

关键词： Phase change random access memory Concurrent computing Computational modeling Costs Memory management Hardware Automatic programming Laboratories DSL Libraries

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Probabilistic models for the guarded command language

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SCIENCE OF COMPUTER programming 1997年第2-3期28卷 171-192页

作者： He, JF Seidel, K McIver, A Oxford University Computing Laboratory Programming Research Group 11 Keble. Road Oxford OX1 3QD UK

The two models presented in this paper provide two different semantics for an extension of Dijkstra's language of guarded commands. The extended language has an additional operator, namely probabilistic choice, which makes it possible to express randomized algorithms. An earlier model by Claire Jones included probabilistic choice but not non-determinism, which meant that it could not be used for the development of algorithms from specifications. Our second model is built on top of Claire Jones' model, using a general method of extending a probabilistic cpo to one which also contains non-determinism. The first model was constructed from scratch, as it were, guided only by the desire for certain algebraic properties of the language constructs, which we found lacking in the second model. We compare and contrast the properties of the two models both by giving examples and by constructing mappings between them and the non-probabilistic model. On the basis of this comparison we argue that, in general, the first model is preferable to the second. (C) 1.97 Elsevier Science B.V.

关键词： probabilistic programming language semantics algebraic laws

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Event-driven hard-particle molecular dynamics using bulk-synchronous parallelism

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COMPUTER PHYSICS COMMUNICATIONS 1997年第1-3期102卷 81-96页

作者： Marin, M Programming Research Group Wolson Building Parks Road Computing Laboratory University of Oxford Oxford OX1 3QD England UK

We describe and analyse a new parallel algorithm for event-driven simulation of hard-particle systems that is based on the ideas of the bulk-synchronous parallel (BSP) model. This model provides a unifying approach for general purpose parallel computing which in addition to efficient computation ensures portability across different parallel architectures. The hard-particle system is divided into regions that are owned by a unique processor. Events involving particles located in the region boundaries are called border zone events and are used to synchronize the parallel operation of the processors. On a P-processor BSP computer the algorithm works doing iterations composed of two phases: the parallel phase where each processor is simultaneously allowed to simulate serially and asynchronously its own region, and the synchronization phase where the occurrence of at most P border zone events is scheduled for the next iteration considering the state of neighboring regions. We show that this algorithm is efficient in practice provided that a sufficiently large hard-particle system is to be simulated.

关键词： molecular dynamics hard particles parallel algorithms

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