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University/Government/Industry Microelectronics Symposium

作者： Chi Hoang M.A. Schmidt Department of Electrical Engineering and Computer Science MicroSystems Technology Laboratories Cambridge MA USA

Summary form only given. For approximately ten years, MIT has supported an undergraduate project laboratory which teaches microfabrication process design. The project laboratory attempts to engage the students in projects which have a end goal of fabrication of a specific novel device, often with an end user that is supporting the laboratory portion of the course. In this paper, we will present the most recent results of teaching this course in the Spring '98 semester. The project this semester was to fabricate an array of micromechanical contactors which could be used in the high-speed testing of integrated circuits. We will describe the execution of the course in detail. A detailed description of the final device design and fabrication will be given with the measured results. We will summarize the lessons learned, particularly in relation to organizing a team of students on one project, and the nuances of working with an industrial sponsor in a course environment.

关键词： laboratories Fabrication Circuit testing Process design Education Springs Micromechanical devices Contactors Integrated circuit testing High speed integrated circuits

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An improved NMOS AC hot-carrier lifetime prediction algorithm based on the dominant degradation asymptote

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IEEE TRANSACTIONS ON ELECTRON DEVICES 1997年第4期44卷 651-658页

作者： Kim, SWA Menberu, B Le, HXP Jiang, WJ Chung, JE Department of Electrical Engineering and Computer Science Microsystems Technology Laboratories Massachusetts Institute of Technology Cambridge MA USA

This study presents a new algorithm for improved prediction of ac hot-carrier lifetime, It is based on identifying and projecting the dominant degradation asymptote, The algorithm accounts for the stress-bias dependence of the hot-carrier degradation rate and the nonlinearity of the degradation time-dependence, Detailed model parameter extraction and lifetime prediction procedures are explained, and applications of the new algorithm demonstrated, Significant differences in the predicted ac-lifetimes are found between the existing and the new algorithms over a wide range of CMOS inverter design parameters, such as the input ramp rate and the load capacitance.

关键词： MOS devices Hot carriers Prediction algorithms Degradation Semiconductor device modeling Predictive models Parameter extraction Inverters Algorithm design and analysis Capacitance

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Analysis and decomposition of spatial variation in integrated circuit processes and devices

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IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING 1997年第1期10卷 24-41页

作者： Stine, BE Boning, DS Chung, JE Microsystems Technology Laboratories Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology Cambridge MA USA

Variation is a key concern in semiconductor manufacturing and is manifest in several forms, Spatial variation across each wafer results from equipment or process limitations, and variation within each die may be exacerbated further by complex pattern dependencies, Spatial variation information is important not only for process optimization and control, but also for design of circuits that are robust to such variation, Systematic and random components of the variation must be identified, and models relating the spatial variation to specific process and pattern causes are needed, In this work, extraction and modeling methods are described for wafer-level, die-level, and wafer-die interaction contributions to spatial variation. Wafer-level estimation methods include filtering, spline, and regression based approaches, Die-level (or intra-die) variation can be extracted using spatial Fourier transform methods;important issues include spectral interpolation and sampling requirements, Finally, the interaction between wafer- and die-level effects is important to fully capture and separate systematic versus random variation;spline- and frequency-based methods are proposed for this modeling, Together, these provide an effective collection of methods to identify and model spatial variation for future use in process control to reduce systematic variation, and in process/device design to produce more robust circuits.

关键词： Semiconductor device modeling Process control Circuits Robust control Spline Semiconductor device manufacture Design optimization Data mining Filtering Fourier transforms

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A flexible, distributed architecture for semiconductor process control and experimentation

A flexible, distributed architecture for semiconductor proce...

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Conference on Open Architecture Control Systems and Standards

作者： Gower, A Boning, D McIlrath, M Microsystems Technology Laboratories Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology Cambridge MA 02139 United States

ISBN: (纸本)0819423149

Semiconductor fabrication requires an increasingly expensive and integrated set of tightly controlled processes, driving the need for a fabrication facility with fully computerized, networked processing equipment. We describe an integrated, open system architecture enabling distributed experimentation and process control for plasma etching. The system was developed at MIT's microsystems technology laboratories and employs in-situ CCD interferometry based analysis in the sensor-feedback control of an Applied Materials Precision 5000 Plasma Etcher (AME5000). Our system supports accelerated, advanced research involving feedback control algorithms, and includes a distributed interface that utilizes the internet to make these fabrication capabilities available to remote users. The system architecture is both distributed and modular: specific implementation of any one task does not restrict the implementation of another. The low level architectural components include a host controller that communicates with the AME5000 equipment via SECS-II, and a host controller for the acquisition and analysis of the CCD sensor images. A Cell Controller (CC) manages communications between these equipment and sensor controllers. The CC is also responsible for process control decisions;algorithmic controllers may be integrated locally or via remote communications. Finally, a System Server manages connections from internet/intranet (web) based clients and uses a direct link with the CC to access the system. Each component communicates via a predefined set of TCP/IP socket based messages. This flexible architecture makes integration easier and more robust, and enables separate software components to run on the same or different computers independent of hardware or software platform.

关键词： distributed architecture in-situ data acquisition semiconductor process control distributed interface

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Architecture for distributed design and fabrication

Architecture for distributed design and fabrication

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Plug and Play Software for Agile Manufacturing

作者： McIlrath, Michael B. Boning, Duane S. Troxel, Donald E. Massachusetts Institute of Technology Microsystems Technology Laboratories Department of Electrical Engineering and Computer Science Cambridge MA 02139 United States

We describe a flexible, distributed system architecture capable of supporting collaborative design and fabrication of semi-conductor devices and integrated circuits. Such capabilities are of particular importance in the development of new technologies, where both equipment and expertise are limited. Distributed fabrication enables direct, remote, physical experimentation in the development of leading edge technology, where the necessary manufacturing resources are new, expensive, and scarce. Computational resources, software, processing equipment, and people may all be widely distributed;their effective integration is essential in order to achieve the realization of new technologies for specific product requirements. Our architecture leverages is essential in order to achieve the realization of new technologies for specific product requirements. Our architecture leverages current vendor and consortia developments to define software interfaces and infrastructure based on existing and merging networking, CIM, and CAD standards. Process engineers and product designers access processing and simulation results through a common interface and collaborate across the distributed manufacturing environment. ©2005 Copyright SPIE - The International Society for Optical engineering.

关键词： Fabrication

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Correction To "M-test: A Test Chip For Mems Material Property Measurement Using Electrostatically Actuated Test Structures"

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Journal of Microelectromechanical Systems 1997年第3期6卷 286-286页

作者： P.M. Osterberg S.D. Senturia Microsystems Technology Laboratories Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology Cambridge MA USA School of Engineering University of Portland Portland OR USA

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A sealed cavity TFR process for RF bandpass filters

A sealed cavity TFR process for RF bandpass filters

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1996 International Electron Devices Meeting

作者： Lutsky, JJ Naik, RS Reif, R Sodini, CG MIT Microsystems Technology Laboratories Department of Electrical Engineering and Computer Science Cambridge 02139 MA United States

ISBN: (纸本)0780333942

Thin film bulk acoustic wave resonators(TFRs) show considerable promise as a silicon compatible integrated solution for RF bandpass filters with center frequencies in the 1-2 GHz range. This paper presents a VLSI compatible sealed cavity TFR process using reactively sputtered AlN as the piezoelectric film. The devices are free-standing and have a fundamental longitudinal resonance at 1.36 GHz with an insertion loss of 3.5 dB, a K-eff(2) of .4%, and a Q(series) of 210.

关键词： Bandpass filters

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A new algorithm for NMOS AC hot-carrier lifetime prediction based on the dominant degradation asymptote

A new algorithm for NMOS AC hot-carrier lifetime prediction ...

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Annual International Symposium on Reliability Physics

作者： S.-W.A. Kim B. Menberu J.E. Chung Department of Electrical Engineering & Computer Science Microsystems Technology Laboratories Massachusetts Institute of Technology Cambridge MA USA

This study presents a new algorithm for improved prediction of AC hot-carrier lifetime. It is based on identifying and projecting the dominant degradation asymptote and accounts for the stress-bias-dependent degradation rate n, and the non-linearity of the degradation time-dependence. Detailed model parameter extraction and lifetime prediction procedures are explained, and applications of the new algorithm demonstrated. Significant differences in the predicted AC-lifetimes are found between the existing and the new algorithms over a wide range of CMOS inverter designs.

关键词： MOS devices Hot carriers Degradation Semiconductor device modeling Prediction algorithms Predictive models Parameter extraction Inverters Algorithm design and analysis computer science

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A sealed cavity TFR process for RF bandpass filters

A sealed cavity TFR process for RF bandpass filters

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International Electron Devices Meeting (IEDM)

作者： J.J. Lutsky R.S. Naik R. Reif C.G. Sodini Department of Electrical Engineering and Computer Science M. I. T. MicroSystems Technology Laboratories Cambridge MA USA

Thin film bulk acoustic wave resonators (TFRs) show considerable promise as a silicon compatible integrated solution for RF bandpass filters with center frequencies in the 1-2 GHz range. This paper presents a VLSI compatible sealed cavity TFR process using reactively sputtered AlN as the piezoelectric film. The devices are free-standing and have a fundamental longitudinal resonance at 1.36 GHz with an insertion loss of 3.5 dB, a K/sub eff//sup 2/ of .4 %, and a Q/sub series/ of 210.

关键词： Radio frequency Band pass filters Piezoelectric films Semiconductor thin films Sputtering Acoustic waves Silicon Very large scale integration Resonance Insertion loss

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THE IMPACT OF NMOSFET HOT-CARRIER DEGRADATION ON CMOS ANALOG SUBCIRCUIT PERFORMANCE

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IEEE JOURNAL OF SOLID-STATE CIRCUITS 1995年第6期30卷 644-649页

作者： CHAN, VH CHUNG, JE Department of Electrical Engineering and Computer Science Microsystems Technology Laboratories Massachusetts Institute of Technology Cambridge MA USA

This study presents some of the first experimental data on the impact of NMOSFET hot-carrier-induced degradation on CMOS analog subcircuit performance, Because of circuit design requirements, most NMOSFET's used for analog applications are biased in the saturation region with a low gate-to-source voltage, Under such operating conditions, in addition to interface states, significant numbers of hole traps are also generated inside the gate oxide, Because acceptor-type interface states are mostly unoccupied in the saturation region, hole traps are found to have a much more significant impact on analog NMOSFET device performance, The hot-carrier-induced degradation of analog subcircuit performance is also found to be quite sensitive to the particular circuit design and operating conditions, Circuit performance and reliability tradeoffs are examined.

关键词： Carrier traps gate oxide Electric circuits Operating conditions CIRCUIT DESIGN metal-oxide-semiconductor field effect transistors Experimental data interface states Saturation Zone Hot carriers

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