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International Conference on Solid State Sensors and Actuators (TRANSDUCERS)

作者： S.D. Senturia Microsystems Technology Laboratories Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology Cambridge MA USA

CAD Systems for microelectromechanical systems (MEMS) require the three-dimensional and multi-energy- domain modeling of mechanical engineering and the planar mask layout and circuit simulation of integrated circuits. Several CAD systems for MEMS are now under development. Challenges include geometric construction from mask and process data, three-dimensional coupled- energy-domain simulation, construction of lumped macro-models, and computer-aided insertion of those macro-models into dynamical simulators. Examples are given based on the MIT MEMCAD system.

关键词： Microelectromechanical systems Solid modeling Micromechanical devices Numerical simulation Context modeling Circuit simulation Computational modeling Transducers Process design Circuit testing

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"Membuilder": An Automated 3D Solid Model Construction Program For Microelectromechanical Structures

"Membuilder": An Automated 3D Solid Model Construction Progr...

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International Conference on Solid State Sensors and Actuators (TRANSDUCERS)

作者： P.M. Osterberg S.D. Senturia Department of Electrical Engineering and Computer Science Microsystems Technology Laboratories Massachusetts Institute of Technology Cambridge MA USA

Designers of microelectromechanical structures (MEMS) need to be able to construct, visualize and analyze robust 3D solid models within a single, convenient and integrated CAD design environment. We now report the completion , of our "MemBuilder" software which accornmodates this need within the I-DEAS Master Series CAD environment. MemBuilder automates the process of 3D solid model construction of MEMS structures starting from user defined process data and 2D mask data. Meryffluilder successfully emulates MEMS structure construction in both surface-micromachined and wafer-bonded processes.

关键词： Solid modeling Emulation Micromechanical devices Etching Solid state circuits Actuators Data visualization Performance analysis Hazards Productivity

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Oxide-field dependence of the NMOS hot-carrier degradation rate and its impact on AC-lifetime prediction

Oxide-field dependence of the NMOS hot-carrier degradation r...

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International Electron Devices Meeting (IEDM)

作者： S.A. Kim B. Menberu T.E. Kopley J.E. Chung Department of Electrical Engineering & Computer Science Microsystems Technology Laboratories Massachusetts Institute of Technology Cambridge MA USA Central Research & Development Siemens AG Munich Germany

This study presents a general relationship between the NMOS hot-carrier degradation rate n and the oxide-electric field at the drain E/sub ox/, which is valid over a wide range of stress-bias conditions and device parameters. Physical mechanisms for this oxide-field dependence are explored. It is also shown that failure to account for the oxide-field dependence of n and the inherent non-linearity of the degradation time dependence can result in significant overestimation of the predicted AC lifetime.

关键词： MOS devices Hot carriers Degradation Stress MOSFETs Voltage Hydrogen computer science laboratories Testing

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FAULT-TOLERANT ASSOCIATE MEMORIES

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SYSTEMS AND computerS IN JAPAN 1995年第7期26卷 1-12页

作者： FUJIWARA, E TANAKA, T Member Faculty of Engineering Tokyo Institute of Technology Tokyo Japan 152 Eui Fujiwara:received his B.S. and M.S. degrees in Electronics Engineering in 1968 and 1970 respectively and his Dr. of Eng. degree in 1981 all from Tokyo Institute of Technology. In 1970 he joined the NTT Musashino Electrical Communication Laboratories and engaged in developing PIPS-1 and PIPS-11 computer systems. In 1988 he joined the Department of Computer Science Tokyo Institute of Technology as an Associate Professor. In 1990 he became a full Professor. He was a Visiting Professor at the Center for Advanced Computer Studies the University of Southwestern Louisiana from June 1985 to July 1986. His current research interests include coding theory for computers fault-tolerant memories VLSI defect-toleranceand WSI systems. He is a co-author ofError Control Coding for Computer Systems(Prentice-Hall1989) EssentiaLF of Error-Correcting Coding Techniques (Academic Press 1990) and other books. Dr. Fujiwara received the Young Engineer Award from the I.E.I.C.E. in 1978 and the Teshima Memorial Research Award in 1991. He is a senior member of the IEEE and a member of the Information Processing Society Japan. Associate Member

Because of its capability of high-speed search, the associative memory (CAM) is expected to be used in a variety of information processing systems. In this paper, novel fault-tolerant techniques which are effective for on-line use are proposed for TLB which is an example of the application of CAM. First, fault and error models of the TLB consisting of the CAM part and the SRAM part are clarified. Then, the fault-tolerant techniques for these faults and errors, such as distance separable technique, cod-ing technique, simplified 1-out-of-n check and graceful degradation, are proposed. The distance separable technique which encodes the data stored in the CAM part is the one which masks the faulty CAM part and prevents errors from propagating to the subsequent circuits. The coding technique checks the one-to-one correspondence between the data in the CAM and those in SRAM by using the SEC-DED code with byte error detection capability, i.e., SEC-DED-SbED code, and at the same time it detects and corrects errors in the data stored in SRAM. The simplified 1-out-of-n check processes association errors. The graceful degradation gives a flag in the faulty memory section and prevents it from being used. The methods proposed in this paper are evaluated from area augmentation and error detection capability perspectives. The results show that the fault-tolerant TLB with 32 virtual address bits, 32 physical address bits and 128 entries gives single fault detection probability of nearly 99 percent with 28 percent area increase.

关键词： CAM TLB DISTANCE SEPARABLE TECHNIQUE CODING TECHNIQUE SIMPLIFIED 1-OUT-OF-N CHECK GRACEFUL DEGRADATION

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Fabrication of Polycrystalline Si 1−x Ge x Films on Oxide for Thin-Film Transistors

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MRS Online Proceedings Library 1994年第1期343卷 679-684页

作者： Julie A. Tsai Andrew J. Tang Rafael Reif Department of Materials Science and Engineering Massachusetts Institute of Technology Cambridge USA Department of Electrical Engineering and Computer Science Microsystems Technology Laboratories Massachusetts Institute of Technology Cambridge USA

Polycrystalline-Si1−xGex films have been formed by various methods on oxide-coated Si substrates at temperatures ≤600°C. Compared to thermal growth, plasma deposition of poly-Si1−xGex promotes smoother films with smaller grains having a 200-dominated texture. Poly-Si1−xGex Alms formed by plasma deposition of amorphous-Si1-xGex followed by a crystallization anneal have an even smoother surface with grain sizes enhanced by an order of magnitude and a weak 111 grain texture. Hydrogen incorporated in amorphous-Si1−xGex evolves completely during crystallization without disrupting the smooth surface morphology. The largest grain sizes (∶1.3μm) are achieved in poly-Si1−xGex films formed by Si+ ion implantation for amorphization with a subsequent recrystallization anneal.

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High-frequency AC hot-carrier degradation in CMOS circuits

High-frequency AC hot-carrier degradation in CMOS circuits

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International Electron Devices Meeting (IEDM)

作者： Vei-Han Chan T.E. Kopley P. Marcoux J.E. Chung Department of Electrical Engineering and Computer Science Microsystems Technology Laboratories Massachusetts Institute of Technology Cambridge MA USA ICBD Technology Development Center Hewlett Packard Company Palo Alto CA USA

The device degradation due to hot carriers generated under high-frequency circuit operation is studied in detail. Two new degradation phenomena are observed at these high frequencies. First, voltage overshoot, due to internal MOSFET parasitic capacitances, causes enhanced hot-carrier degradation. Second, the quasi-static approximation is found to be invalid at high frequencies. For NMOSFETs, fast voltage transitions are found to induce different degradation dynamics; for PMOSFETs, donor-type interface-state generation and electron detrapping both become significant.< >

关键词： Hot carriers Degradation Circuit testing MOSFETs Voltage Stress MOS devices Frequency CMOS technology Logic testing

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Growth and Characterization of Silicon-Germanium Films on Oxide by VLPCVD/PE-VLPCVD

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MRS Online Proceedings Library 1993年第1期317卷 603-608页

作者： Tsai, Julie A. Reif, Rafael Department of Materials Science and Engineering Microsystems Technology Laboratories Massachusetts Institute of Technology Cambridge USA Department of Electrical Engineering and Computer Science Microsystems Technology Laboratories Massachusetts Institute of Technology Cambridge USA

Results of Si1−xGex deposition on oxide-coated Si substrates using a PE-VLPCVD (Plasma-Enhanced Very-Low-Pressure Chemical Vapor Deposition) reactor are presented. Thin layers of poly-Si1−xGex deposited with SiH4 and GeH4 at ≤ 600°C had low C and O levels. Two growth modes were examined at 500°C: plasma-initiated thermal growth (VLPCVD) and full plasma-enhanced deposition (PE-VLPCVD). In both cases, Ge incorporation increases sublinearly with gas ratio, growth rates increase with Ge content, and the transition temperature between polycrystalline and amorphous deposition is lower for Si1−xGex than Si. On the other hand, compared to thermal growth, plasma-enhanced deposition promotes not only higher growth rates but also improved structural properties such as smoother surface morphology, more columnar and oriented grains, and the unique feature of direct deposition onto oxide.

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Two-stage hot-carrier degradation and its impact on submicron LDD NMOSFET lifetime prediction

Two-stage hot-carrier degradation and its impact on submicro...

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International Electron Devices Meeting (IEDM)

作者： Vei-Han Chan J.E. Chung Microsystems Technology Laboratories Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology Cambridge MA USA

The device degradation of oxide-spacer LDD NMOS transistors due to hot carriers is studied in detail. It is found that the observed saturation in the degradation time dependence is due to a combination of an increase in the series resistance in the lightly-doped drain region, and a reduction of the carrier mobility in the channel and subdiffusion regions. Because the increase in series resistance eventually saturates, an asymptotic degradation rate coefficient can be used to extract a more accurate and consistent value of LDD NMOS lifetime.< >

关键词： Hot carriers Degradation MOSFET circuits MOS devices Stress Charge pumps Interface states electrical resistance measurement Voltage measurement Electric resistance

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The impact of hot-electron degradation on CMOS analog subcircuit performance

The impact of hot-electron degradation on CMOS analog subcir...

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Custom Integrated Circuits Conference (CICC)

作者： Vei-Han Chan B.W. Scharf J.E. Chung Department of Electrical Engineering and Computer Science Microsystems Technology Laboratories Massachusetts Institute of Technology Cambridge MA USA Analog Devices Inc.orporated Wilmington MA USA

Experimental data on CMOS analog circuit degradation due to hot-electron effects are presented. Because of circuit design constraints, most MOSFETs used for analog applications are biased in the saturation region with low gate voltage. Under such operating conditions, in addition to interface states, significant numbers of hole traps are also generated inside NMOSFETs. Because acceptor-type interface states are mostly unoccupied in the saturation region, hole traps are found to have a much more significant impact on NMOSFET performance. It is demonstrated that analog subcircuit performance degradation is quite sensitive to the particular circuit design and operating conditions. Circuit performance and reliability tradeoffs are also evaluated.

关键词： Degradation Analog circuits Interface states Voltage Stress MOSFETs CMOS analog integrated circuits Circuit synthesis Circuit optimization Digital circuits

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An approach to the direct analysis of transient stability

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European Transactions on electrical Power 1993年第3期3卷 241-248页

作者： Djukanovic, M.B. Sobajic, D.J. Pao, Y.‐H. Miodrag B. Djukanovic (1959) received his B.S. M.Sc. and Ph.D. degrees in Electrical Engineering from the University of Belgrade/Yugoslavia in 1982 1985 and 1992 respectively specializing in electric power systems. In 1984 he joined the Electrical Engineering Institute “Nikola Tesla” in Belgrade where he was working on the scientific studies in the field of power systems planning operation and control. In 1985 and 1990 he was appointed as a research scholar at the Royal Institute of Technology Stockholm and Case Western Reserve University Cleveland Ohio. His major in- terests are in the area of power system analysis steady-state and dynamic security and application of neural networks in electric power systems. (Electrical Engineering Institute “Nicola Tesla” ul. Koste Glavinica 8A YU-11000 Belgrad T +3811/2351-619 Fax + 3811/2351-823) Dejan J. Sobajic (1949) received the B.S.E.E. and the M.S.E.E. degrees from the University of Belgrade/Yugoslavia in 1972 and 1976 respectively and the Ph.D. degree from Case Western Reserve University Cleveland Ohio in 1988. At present he is with the Department of Electrical Engineering and Applied Physics Case Western Reserve University Cleveland. He is also the Engineering Manager of A1 WARE Inc. Cleveland. His current research interests include power system operation and control neuralnet systems and adaptive control. He is a member of the IEEE Task Force on Neural-Network Applications in Power Systems and of the IEEE Intelligent Controls Committee. He is the Chairman of the International Neural-Networks Society Special Interest Group on Power Engineering. (Case Western Reserve University Department of Electrial Engineering and Computer Sciences Glennan Building Ohio 44 106 USA T + 1216/421-2380 Fax +1216/368-8776) Yoh-Han Pao (1922) has been a Professor of Electrical Engineering and Computer Science at Case Westem Reserve University (CWRU) Cleveland Ohio since 1967. He has served as chairman of the University's Electrical Engineering Department

The Transient Energy Function (TEF) method has been intensely investigated over the last decade as a reliable and accurate tool for transient stability assessment of multimachine power systems. In this paper we propose the Potential Energy Boundary Surface (PEBS) based method for direct analysis of transient stability. The critical value of transient energy and the Critical Clearing Time (T_CCT) are evaluated without the need for successive calculation and memorization of the system kinetic and potential energy values along the sustained fault trajectory. The method is used for determination of output features in the training phase of the neural‐net based transient security assessment. The proposed approach is tested on the well‐known ten‐generator New England test system demonstrating the validity and accuracy of obtained results. Copyright © 1993 John Wiley & Sons, Ltd.

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