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检索条件"机构=3D Systems Packaging Research Center Georgia Institute of Technology"

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Inverse design of Embedded Inductor with Hierarchical Invertible Neural Transport Net 31

Inverse Design of Embedded Inductor with Hierarchical Invert...

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IEEE 31st Conference on Electrical Performance of Electronic packaging and systems (EPEPS)

作者： Akinwande, Oluwaseyi Bhatti, Osama Waqar Swaminathan, Madhavan School of Electrical and Computer Engineering 3D Systems Packaging Research Center Georgia Institute of Technology Atlanta USA School of Material Science and Engineering 3D Systems Packaging Research Center Georgia Institute of Technology Atlanta USA

ISBN: (数字)9781665450751

ISBN: (纸本)9781665450751

Heterogeneous integration of voltage regulators in power delivery networks is a growing trend that employs embedded inductor as a key component in significantly improving the power distribution. In this work, we propose a neural network framework called the hierarchical invertible neural transport for the inverse design of an embedded inductor. With this invertible method, we obtain the probability distributions of the parameters of the embedded inductor design space that most likely satisfy the desired specifications. We also learn the impedance response for free in the forward design. In the forward design, our results show a 2.14% normalized mean square error when compared with the output response of a fullwave EM simulator.

关键词： power delivery inverse design emdedded inductor neural networks transport maps

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Reinforcement Learning for the Optimization of Power Plane designs in Power delivery Networks 31

Reinforcement Learning for the Optimization of Power Plane D...

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IEEE 31st Conference on Electrical Performance of Electronic packaging and systems (EPEPS)

作者： Han, Seunghyup Bhatti, Osama Waqar Swaminathan, Madhavan School of Electrical and Computer Engineering 3D Systems Packaging Research Center (PRC) Georgia Institute of Technology Atlanta GA USA School of Material Science and Engineering 3D Systems Packaging Research Center (PRC) Georgia Institute of Technology Atlanta GA USA

ISBN: (数字)9781665450751

ISBN: (纸本)9781665450751

This paper proposes a deep deterministic policy gradient (ddPG) based method to optimize the power plane in power delivery networks (PdNs). The proposed method considers the degrees of freedom of a plane design in a layer, determining the parameters for creating a power plane. The results show that the proposed method can provide an optimized power plane design even in a plane layer with a restricted region.

关键词： deep deterministic policy gradient (ddPG) Power plane Power delivery network Reinforcement learning (RL)

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Novel zero side-etch process for <1μm package redistribution layers 72

Novel zero side-etch process for <1μm package redistributio...

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72nd IEEE Electronic Components and technology Conference, ECTC 2022

作者： Nimbalkar, Pratik Bhaskar, Pragna Blancher, Christopher Kathaperumal, Mohanalingam Swaminathan, Madhavan Tummala, Rao Georgia Institute of Technology 3D Systems Packaging Research Center AtlantaGA United States

ISBN: (纸本)9781665479431

Higher bandwidth interconnections are critical for More-than-Moore systems. This requires higher IO-density package redistribution layers (RdL) for faster chip-to-chip communication. Scaling down RdL critical dimensions is thus an essential research component for advanced packaging. There are numerous challenges pertaining to the further miniaturization of package RdL. Copper seed-layer etching is one of the most important steps in traditional semi-additive processing (SAP). It is very critical to accurately control the copper etch rate for achieving fine-line redistribution layers (RdL). However, due to the isotropic nature of the chemical etchants, it has proven to be the main bottleneck in developing fine line RdL using SAP. Using the traditional wet etchants, over-etching of copper seed-layer results in large reductions in the dimensions of RdL traces. There are reports in literature on using dry etching for copper seed removal with tight process control. However, dry etching does not provide the throughput and cost advantage that comes with wet processing. This paper demonstrates a novel zero side-etch RdL patterning process using the traditional wet SAP. A titanium barrier is coated on the sidewalls of copper RdL traces. Traditional wet etching is then performed to remove the copper seed-layer. Over-etching can be performed to ensure complete removal of seed-layer. The barrier protects the copper traces from the etching effect of chemicals thus preventing the changes in the RdL linewidth and spacing. After seed-layer removal, the titanium barrier can be completely removed from the RdL traces using a wet process. This process enables the use of SAP for achieving RdL critical dimensions lower than 1 μm. © 2022 IEEE.

关键词： Titanium

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Organic and Hybrid Nanoscale Films for Low Loss direct Glass-Copper Metallization

Organic and Hybrid Nanoscale Films for Low Loss Direct Glass...

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Electronic Components and technology Conference (ECTC)

作者： Sai Saravanan Ambi Hyunggyu Park Lakshmi Narasimha Vijay Kumar Lila dahal Mohanalingam Kathaperumal Mark d. Losego 3D Systems Packaging Research Center Georgia Institute of Technology Atlanta USA

ISBN: (数字)9798331539320

ISBN: (纸本)9798331539337

direct patterning of copper (Cu) traces on glass core substrates suffers from poor adhesion, stress induced cracking, thus requiring a thick build-up layer which increases the overall size of the package. In addition, a smooth interface between glass-Cu is required to minimize conduction losses in the GHz frequency regime and overcome lithography constraints to achieve < ${2 \mu \mathrm{m}}$ redistribution layer (RdL) lines and spaces. However, low-roughness interfaces can have lower adhesion strength due to poor mechanical interlocking. Thus, this study examines the use of smooth nanoscale adhesion promoters (NAPs) to improve the glass-Cu adhesion. The NAPs investigated include thin films of spin coated cyanoethyltrimethoxysilane (CNETMS), plasma enhanced chemical vapor deposited (PECVd) silicon nitride (SiN y ), and PECVd silicon oxynitrides (SiO x N y ) on alkaline-free boro-aluminosilicate glass substrates. Low stress copper films (~ 25 μm thickness) were electroplated onto the NAPs and their peel strengths were measured to evaluate their adhesion performance. High peel strength of ~ 8 and ~ 6.5 N/cm were achieved from ~ 75 and ~ 88 nm thick SiO 2 N (O : N ~1.93:1) and SiN y NAPs respectively, compared to bare glass adhesion of ~ 0.8 N/cm (without any plasma pretreatment and seed layer annealing). Roughness and peel strength were also compared with low loss industry standard dielectrics used in semiconductor packaging.

关键词： Adhesives Metallization Films Glass Silicon Nanoscale devices Plasmas Copper Stress Substrates

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2d Spectral Transposed Convolutional Neural Network for S-Parameter Predictions 31

2D Spectral Transposed Convolutional Neural Network for S-Pa...

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IEEE 31st Conference on Electrical Performance of Electronic packaging and systems (EPEPS)

作者： Guo, Yiliang Li, Xingchen Swaminathan, Madhavan 3D Systems Packaging Research Center (PRC) School of Electrical and Computer Engineering Georgia Institute of Technology Atlanta GA USA

In packaging problems, S-parameter predictions are necessary. Machine learning methods lead to dimensionality related challenges which we address here through spectral transposed convolutional neural network using 2d ... 详细信息

ISBN: (数字)9781665450751

ISBN: (纸本)9781665450751

关键词： microvia interconnection convolutional neural network up-sampling

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Characterization of Warpage of Ultra-Low-K dielectric Materials and Correlation with Modulus and Coefficient of Thermal Expansion

Characterization of Warpage of Ultra-Low-K Dielectric Materi...

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Electronic Components and technology Conference (ECTC)

作者： Mohanalingam Kathaperumal Pragna Bhaskar Austin J. Toro Pratik Nimbalkar Lila dahal Muhannad S. Bakir 3D Systems Packaging Research Center Georgia Institute of Technology Atlanta GA

ISBN: (数字)9798350375985

ISBN: (纸本)9798350375992

Advanced high-performance computing (HPC) and artificial intelligence (AI) systems demand arger glass package systems that may extend to 200 mm × 200 mm package size. This large package sizes invariably require stringent properties of the insulation/build-up layers consisting of low to Ultra-low K (ULK) dielectric polymers. The inclusion of ULK polymer layers is of great importance to improve latency, signal integrity and energy per bit owing to their reduced capacitance. However, ULK polymers are typically without any added filler particles and hence need to be thoroughly characterized to realize a good control on yield ad reliability. Particularly in the case of fine line RdL (< 2 μm Lines/Spaces) both RdL critical dimensions yield and reliability depend upon the warpage, surface roughness of the dielectric insulation layer. Hence it is of great significance to measure the warpage of the ULK layer in order to understand the influence of warpage on yield of fine line RdL across the entire length of the package. By virtue of the molecular groups present in ULK polymers which consist of moderately fluorinated to perfluorinated moieties in the backbone, evaluation of potential correlation between warpage to yield, adhesion strength and surface roughness is of great importance. The ULK polymers investigated in this paper include photo-imageable and non-photo-imageable dielectric polymers.

关键词： Fabrication Thermal expansion Correlation Glass Surface roughness dielectrics Rough surfaces

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Evaluation of Parylene-HT as dielectric for Application in Advanced Package Substrates

Evaluation of Parylene-HT as Dielectric for Application in A...

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Electronic Components and technology Conference (ECTC)

作者： Pratik Nimbalkar Mercy Aguebor Mohanalingam Kathaperumal Madhavan Swaminathan Rao Tummala 3D Systems Packaging Research Center Georgia Institute of Technology Atlanta USA Dept. of Electrical Engineering 3D Systems Packaging Research Center Pennsylvania State University

Polymer dielectrics having low dielectric constants are necessary for next-generation package substrates to achieve lower losses and higher bandwidth densities. Conventional silica-filled dielectrics have higher dielectric constants due to the silica fillers. Therefore, it is important to explore novel dielectric materials for next-generation package substrates that have lower dielectric constants. Parylenes have a unique set of properties such as- very low moisture absorption, low gas permeability, conformal deposition, and heat resistance. Some parylenes also have a very low dielectric constant, low dielectric dissipation losses and low roughness that make them attractive as dielectrics for application in advanced package substrates. Amongst all parylenes, Parylene-Hthas the lowest dielectric constant $(\mathrm{d}_{k})$ of 2.17 and dissipation factor $(\mathbf{d}_{f})$ of 0.001 at 1 MHz, thus making it attractive for high-frequency applications. However, there are several challenges associated with the use of polymer dielectrics in package substrates such as- adhesion to Cu, via formation ability, processability, mechanical reliability and electrical reliability. This paper evaluates Parylene- Htwith respect to all these challenges.

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Maskless Lithography for High-density Package Redistribution Layers

Maskless Lithography for High-Density Package Redistribution...

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Electronic Components and technology Conference (ECTC)

作者： Prahalad Murali Pratik Nimbalkar Mohanalingam Kathaperumal Mark d. Losego Rao Tummala Madhavan Swaminathan 3D Systems Packaging Research Center Georgia Institute of Technology Atlanta USA 3D Systems Packaging Research Center & Dept. of Electrical Engineering Pennsylvania State University

Heterogeneous integration of chiplets requires high-density fine line/space (L/S) interconnections to enable system scaling. However, as Moore's law for transistors slows down, the dies are disaggregated based on their specific functions thereby increasing the package sizes to accommodate various dies of different functionalities. To enable a high-density redistribution layer (RdL) in the package, this paper studies the fine-line patterning capability of maskless aligner systems. The paper evaluates the smallest achievable feature size on four different thicknesses namely 5 $\mu \mathrm{m}, 7 \mu \mathrm{m}, 25 \mu \mathrm{m}$ and 80 $\mu \mathrm{m}$ of dry film photoresists (PRs). This work also investigates the effect of dose and defocus on photoresists. Two of the photoresists (5 μm and 80 $\mu \mathrm{m})$ are positive tone and the other 2 are negative tone. The finest L/S obtained was 1.5μm with the positive tone 5 $\mu \mathrm{m}$ dry film photoresist, 3 $\mu \mathrm{m}$ using the 7 $\mu \mathrm{m}$ negative tone and 20 μm using the 80 μm positive tone resist. This paper also investigates the throughput of the maskless aligners based on the dose, exposure area, and pattern density.

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Broadband characterization of 6G microelectronics packaging materials: EN-A1 alkali-free boroaluminasilicate glass substrates

Broadband characterization of 6G microelectronics packaging ...

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2023 Conference on Lasers and Electro-Optics Europe and European Quantum Electronics Conference, CLEO/Europe-EQEC 2023

作者： Zhai, Min Shi, Haolian Swaminathan, Madhavan Locquet, Alexandre Citrin, d.S. Georgia Tech-CNRS IRL2958 Georgia Tech Lorraine 2 Rue Marconi Metz57070 France School of Electrical and Computer Engineering Georgia Institute of Technology AtlantaGA30332 United States 3D Systems Packaging Research Center Georgia Institute of Technology AtlantaGA30332 United States

ISBN: (纸本)9798350345995

With the commercial deployment of 5G and 6G wireless communication networks, high-frequency packaging is crucial to the stringent performance requirements of THz wireless components and integrated circuits (ICs). To date, owing to the high stability in service and manufacturing, tailorable coefficients of thermal expansion (CTE) matching to Si (3.8×10-6/K versus 3.3×10-6/K), as well as excellent scalability, glasses have attracted significant attention as a promising substrate material for packaging future-generation network systems. In this work, EN-A1 alkali-free boroaluminasilicate glass, a novel 6G microelectronic packaging material from Asahi Glass Corporation, is characterized by terahertz (THz) time-domain spectroscopy. A Fabry Pérot cancellation procedure and 5th-order polynomial curving fitting [1,2], are implemented prior to dielectric-parameter extraction to suppress oscillations that otherwise appear at frequencies ν′, and loss tangent tanδ(ν)] of EN-A1 glass are obtained from 200 GHz to 2.5 THz. We find that the value of the refractive index n(ν) decreases slightly from 2.466 at 200 GHz to 2.2 at 2.5 THz, the value of the absorption coefficient α(ν) increases dramatically from 5.68 cm-1 at 200 GHz to 115.6 cm-1 at 2.5 THz, the value of the permittivity Ε′ decreases from 6 at 200 GHz to 4.82 at 2.5 THz, and the value of the loss tangent tanδ increases from 0.048 at 200 GHz to 0.093 at 2.5 THz, respectively. Although dielectric characterization was carried out on ABF/EN-A1 glass/ABF stackups from 20 to 170 GHz in Ref. [3], we extend the work there by providing the first broadband material characterization of bare EN-A1 glass substrate from 200 GHz to 2.5 THz. © 2023 IEEE.

关键词： Glass

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Effect of Surface Roughness of Polymer dielectric Materials on Resolution of Fine Line Features

Effect of Surface Roughness of Polymer Dielectric Materials ...

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Electronic Components and technology Conference (ECTC)

作者： Pragna Bhaskar Mohan Kathaperumal Christopher Blancher Mark Losego Madhavan Swaminathan 3D Systems Packaging Research Center School of Material Science and Engineering Georgia Institute of Technology Atlanta USA 3D Systems Packaging Research Center School of Electrical and Computer Engineering Georgia Institute of Technology Atlanta USA 3D Systems Packaging Research Center Georgia Institute of Technology Atlanta USA Department of Electrical Engineering Pennsylvania State University University Park USA

High density interconnects is a key factor for achieving high bandwidth which is required for AI and high performance compute applications. The high density interconnects can be achieved by, 1) fine lines and spaces in a metal layer, or 2) a stack-up consisting of multiple redistribution layers with not so fine lines and spaces. Fabrication of fine lines and spaces is conventionally achieved by advanced lithography and photoresists. However, in order to attain fine lines and spaces formation, the resists and the following processes should lead to a smooth surface which will yield fine lines and spaces. demonstration of lines and spaces (L/S) has been a method to evaluate new dielectrics, photoresists and lithography processes. Adhesion between copper and polymer is an important factor determining the stability of these copper lines on the polymer as the substrate goes through different processes such as photoresist stripping and seed layer etching. Several methods have been employed to improve the adhesion between copper and polymer, the most important among them being plasma treatment. This method relies on mechanical roughening of the surface which results in interlocking between the metal and polymer to improve adhesion. However, there have also been reports indicating that excessive roughness resulting in the detachment of copper traces from the substrate. Therefore, it is important to study how the roughness of the dielectric influences the resolution of fine line features. This paper presents results on the effect of surface roughness of the laminated dielectrics on the resolution of lines and spaces. Ultra-low-k (ULK) dielectric materials having dielectric constants ≤ 3 are selected for this study in addition to an industry standard dielectric material for comparison. These ULK materials were considered owing to their significance as build-up layers in 2.5d interposers with multiple redistribution layers (RdL). However, with their decreasing dielectric consta

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