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FSS: algorithm and neural network accelerator for style transfer

Science China(Information Sciences) 2024年第2期67卷 253-266页

作者： Yi LING Yujie HUANG Yujie CAI Zhaojie LI Mingyu WANG Wenhong LI Xiaoyang ZENG State Key Laboratory of ASIC & System Fudan University Shanghai Explore X Technology Co. Ltd.

Neural networks(NNs), owing to their impressive performance, have gradually begun to dominate multimedia processing. For resource-constrained and energy-sensitive mobile devices, an efficient NN accelerator is necessary. Style transfer is an important multimedia application. However, existing arbitrary style transfer networks are complex and not well supported by current NN accelerators, limiting their application on mobile devices. Moreover, the quality of style transfer needs improvement. Thus, we design the Fast Style system(FSS), where a novel algorithm and an NN accelerator are proposed for style transfer. In FSS, we first propose a novel arbitrary style transfer algorithm, Fast Style. We propose a light network that contributes to high quality and low computational complexity and a prior mechanism to avoid retraining when the style changes. Then, we redesign an NN accelerator for Fast Style by applying two improvements to the basic NVIDIA deep learning accelerator(NVDLA) architecture. First, a flexible dat FSM and wt FSM are redesigned to enable the original data path to perform other operations(including the GRAM operation)by software programming. Moreover, statistics and judgment logic are designed to utilize the continuity of a video stream and remove the data dependency in the instance normalization, which improves the accelerator performance by 18.6%. The experimental results demonstrate that the proposed Fast Style can achieve higher quality with a lower computational cost, making it more suitable for mobile devices. The proposed NN accelerator is implemented on the Xilinx VCU118 FPGA under a 180-MHz clock. Experimental results show that the accelerator can stylize 512×512-pixel video with 20 FPS, and the measured performance reaches up to 306.07 GOPS. The asic implementation in TSMC 28 nm achieves about 22 FPS in the case of a 720-p video.

关键词： neural network accelerator style transfer neural network deep learning

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A MIMO Neural Network Integrated with Maximum Likelihood Phase Recovery for Transoceanic Coherent Transmission

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Journal of Lightwave Technology 2025年第12期43卷 5536-5544页

作者： Wang, Kaihui Wang, Chen Zheng, Tianqi Long, Jianyu Sang, Bohan Zhou, Wen Yu, Jianjun Fudan University State Key Laboratory of ASIC and System School of Information Science and Technology Shanghai200433 China

We proposed a low-complexity multi-input multi-output neural network integrated with a maximum likelihood phase recovery algorithm (MIMO-NN-BMLPR), which is adopted in long-haul coherent optical communication. Neural network based equalization can effectively overcome the nonlinear distortions induced during long-haul transmission. However, the forward neural network equalizer is difficult to track the phase of coherent optical signals. We integrate an additional maximum likelihood phase recovery layer with the MIMO-NN structure so that the phase noise can be compensated. In this work, 8-channel 100-GBaud dual-polarization (DP) PS-16QAM signals are successfully transmitted over 6400km and satisfy the normalized generalized mutual information (NGMI) threshold at 0.86. The proposed MIMO-NN-BMLPR integrates the low-complexity phase estimation with the NNE to improve the performance. Compared with the traditional DSP structure, the proposal prolongs the distance by 48.84% with a 39.80% complexity reduction. © 1983-2012 IEEE.

关键词： Optical communication

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A Ferroelectric Domain-Wall Transistor

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Chinese Physics Letters 2023年第3期40卷 82-86页

作者：欧阳俊孙杰李一鸣江安全 State Key Laboratory of ASIC&System School of MicroelectronicsFudan UniversityShanghai 200433China

On the basis of novel properties of ferroelectric conducting domain walls,the domain wall nanoelectronics emerges and provides a brand-new dimension for the development of high-density,high-speed and energy-efficient *** in-memory computing,three-terminal devices with both logic and memory functions such as transistors purely based on ferroelectric domain walls are urgently ***,a prototype ferroelectric domain-wall transistor with a well-designed coplanar electrode geometry is demonstrated on epitaxial Bi Fe O_(3)thin *** the logic function,the current switching between on/off states of the transistor depends on the creation or elimination of conducting domain walls between drain and source *** the data storage,the transistor can maintain nonvolatile on/off states after the write/erase operations,providing an innovative approach for the development of the domain wall nanoelectronics.

关键词： drain walls ferroelectric

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Experimental demonstration of 220-GHz terahertz signals wireless transmission over 4.6 km

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Science China(Information Sciences) 2025年第1期68卷 386-388页

作者： Yi WEI Jianjun YU Mingxu WANG Xiongwei YANG Qiutong ZHANG Jingwen TAN Bing ZHANG Ying WU Yang HAN Peng TIAN Wen ZHOU Kaihui WANG Feng ZHAO State Key Laboratory of ASIC and System Key Laboratory for Information Science of Electromagnetic Waves (MoE)School of Information Science and Technology Fudan University School of Electronic Engineering Xi'an University of Posts and Telecommunications

The advancement of terahertz (THz) communication technology drives the evolution of wireless communication systems,offering novel pathways and technical means for the development of future 6G communication *** wireless communication systems are often constrained by bandwidth limitations of electronic devices in high frequency ***,THz communication technology leverages the characteristics of electromagnetic waves to transcend these limitations,enabling communication athigher frequencies and wider bandwidths.

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Ferroelectric domain wall memory

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Chinese Physics B 2023年第12期32卷 14-20页

作者：李一鸣孙杰江安全 State Key Laboratory of ASIC&System School of MicroelectronicsFudan UniversityShanghai 200433China

Ferroelectric domain walls appear as sub-nanometer-thick topological interfaces separating two adjacent domains in different orientations,and can be repetitively created,erased,and moved during programming into different logic states for the nonvolatile memory under an applied electric field,providing a new paradigm for highly miniaturized low-energy electronic *** some specific conditions,the charged domain walls are conducting,differing from their insulating bulk *** the past decade,the emergence of atomic-layer scaling solid-state electronic devices is such demonstration,resulting in the rapid rise of domain wall *** review aims to the latest development of ferroelectric domain-wall memories with the presence of the challenges and opportunities and the roadmap to their future commercialization.

关键词： domain wall memory ferroelectric

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An Adaptive Threshold Analog Front-End Circuit for Direct ToF LiDAR 17

An Adaptive Threshold Analog Front-End Circuit for Direct To...

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17th IEEE International Conference on Solid-state and Integrated Circuit Technology, ICSICT 2024

作者： Guo, Jianping Zeng, Xiaoyang Li, Wenhong Wang, Mingyu Fudan University State-key Laboratory of ASIC and system Shanghai201203 China

ISBN: (纸本)9798350361834

The analog front-end (AFE) circuit of the light detection and ranging (LiDAR) receivers need to provide time-of-flight (ToF) when the laser echo arrives. Accurate ToF is crucial for the ranging accuracy of LiDAR receivers. However, targets with different reflectivity will give different timing results even at the same distance due to the light intensity. This paper proposes an AFE circuit for LiDAR receiver. This AFE circuit can adaptively adjust the threshold based on photocurrent to reduce walk error under different light intensities. Proposed AFE is implemented in 55nm CMOS process. Simulation results show that within the photocurrent range of 3 to 20 uA, the timing error is less than 0.8 ns. © 2024 IEEE.

关键词： Avalanche diodes

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Multi-Sampling Mode CDAC Design for a 12-Bit 200MS/s Pipelined-SAR ADC 17

Multi-Sampling Mode CDAC Design for a 12-Bit 200MS/s Pipelin...

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17th IEEE International Conference on Solid-state and Integrated Circuit Technology, ICSICT 2024

作者： Zhang, Tianyu Ye, Fan Ma, Shunli Fudan University State-key Laboratory of ASIC and System Shanghai200433 China

ISBN: (纸本)9798350361834

This paper proposes a multi-sampling mode capacitor DAC (CDAC) for a 12-bit 200MS/s pipelined-SAR ADC, addressing the issue of overfitting in neural network-based calibrations. By implementing normal, offset, and proportional sampling modes, the design ensures the linearity of the ADC's transfer function. The proposed CDAC utilizes a bottom-plate sampling method and a high-linearity bootstrap circuit. Simulation results demonstrate that the proposed ADC achieves an SFDR of around 75dB and an ENOB of approximately 10.8bits across all sampling modes, validating the effectiveness of the design in enhancing ADC performance. © 2024 IEEE.

关键词： Printed circuit boards

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A 250MS/s, 12 Bit Pipeline-SAR ADC Using Coarse-Fine Ring Amplifier 17

A 250MS/s, 12 Bit Pipeline-SAR ADC Using Coarse-Fine Ring Am...

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17th IEEE International Conference on Solid-state and Integrated Circuit Technology, ICSICT 2024

作者： Liu, Linghao Ren, Junyan Ye, Fan Fudan University State Key Laboratory of ASIC and System Department of Microelectronics Shanghai China

ISBN: (纸本)9798350361834

The ring amplifier is an energy effective choice for high performance pipeline ADC. However, sensitivity to process, supply voltage and temperature (PVT) variations and complex stability mechanism make it less practical. This brief introduces a coarse-fine ring amplifier (CFRingAmp) that allows individual designs of large-signal and small-signal processes. With a large and a smaller dead-zones switched by the self-detect-and-switch block, both stability and accuracy are well designed over corners. Furthermore, a 250MS/s, 12-bit pipeline-SAR ADC is implemented adopting the proposed CFRingAmp. Simulated in 28nm CMOS, the ADC achieves an SNDR of 64.1 dB and an SFDR of 74.9 dB over corners at Nyquist frequency while consuming 4.5mW, resulting a Walden figure-of merit (FoM) of 12.7 fJ/conversion step. © 2024 IEEE.

关键词： CMOS integrated circuits

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Two-dimensional complementary gate-programmable PN junctions for reconfigurable rectifier circuit

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Nano Research 2023年第1期16卷 1252-1258页

作者： Zhe Sheng Yue Wang Wennan Hu Haoran Sun Jianguo Dong Rui Yu David Wei Zhang Peng Zhou Zengxing Zhang State Key Laboratory of ASIC and System School of MicroelectronicsFudan UniversityShanghai 200433China National Integrated Circuit Innovation Center Shanghai 201203China

The unique features of ambipolar two-dimensional materials open up a great opportunity to build gate-programmable devices for reconfigurable circuit applications,e.g.,PN junctions for rectifier ***,current-reported rectifier circuits usually consist of one gate-programmable PN junction as the rectifier and one resistor as the load,which are not conductive to voltage output and large-scale *** we propose an approach of complementary gate-programmable PN junctions to assemble reconfigurable rectifier circuit,which include two symmetric back-to-back black phosphorus(BP)/hexagonal boron nitride(h-BN)/graphene heterostructured semi-gate field-effect transistors(FETs)and perform complementary NP and PN junction like complementary metal-oxide-semiconductor(CMOS)*** investigation exhibits that the circuit can effectively reconfigure the circuit with/without rectifying ability,and can process alternating current(AC)signals with the frequency prior 1 KHz and reconfiguration speed up to 25μ*** also achieve the reconfigurable rectifier circuit memory via complementary semi-floating gate FETs *** complementary configuration here should be of low output impedance and low static power consumption,being beneficial for effective voltage output and large-scale integration.

关键词： two-dimensional(2D)material PN junction rectifier circuit complementary configuration

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A field-effect WSe_(2)/Si heterojunction diode

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Chinese Physics B 2023年第1期32卷 592-597页

作者：余睿盛喆胡文楠王越董建国孙浩然程增光张增星 State Key Laboratory of ASIC and System School of MicroelectronicsFudan UniversityShanghai 200433China National Integrated Circuit Innovation Center Shanghai 201203China

It is significant to develop a heterogeneous integration technology to promote the application of two-dimensional(2D)materials in silicon roadmap. In this paper, we reported a field-effect WSe_(2)/Si heterojunction diode based on ambipolar 2D WSe_(2) and silicon on insulator(SOI). Our results indicate that the device exhibits a p–n diode behavior with a rectifying ratio of ~300 and an ideality factor of 1.37. As a photodetector, it has optoelectronic properties with a response time of 0.13 ms, responsivity of 0.045 A/W, detectivity of 4.5×10~(10) Jones and external quantum efficiency(EQE) of 8.9 %.Due to the ambipolar behavior of the WSe_(2), the rectifying and optoelectronic properties of the heterojunction diode can be modulated by the gate electrical field, enabling various potential applications such as logic optoelectronic devices and neuromorphic optoelectronic devices for in-sensor computing circuits. Thanks to the process based on the mature SOI technique, our field-effect heterojunction diode should have obvious advantages in device isolation and integration.

关键词： two-dimensional material ambipolar semiconductor field-effect transistor optoelectronic device

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