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Proton antagonist membrane towards exclusive CO_(2)reduction

Nano Research 2023年第4期16卷 4589-4595页

作者： Taishi Xiao Yao Ma Shicheng Zeng Xiang Yao Tong Ye Hongbin Li Wei Li Zhengzong Sun Department of Chemistry and Shanghai Key Laboratory of Molecular Catalysis and Innovative Materials Fudan UniversityShanghai 200433China School of Microelectronics and State Key Laboratory of ASIC and System Fudan UniversityShanghai 200433China

Membrane electrode assembly reactor offers great promise toward practical CO_(2)***,traditional proton exchange membrane possesses strong acidic chemical environment,which facilitates undesired hydrogen evolution *** we report a proton antagonist strategy,through which the proton diffusion pathways have been severely impeded by Na+cation to produce an alkaline-rich *** this new membrane electrode assembly,we can significantly suppress the hydrogen evolution and achieve a Faradaic efficiency of 95.7%for CO with 51.5%energy *** addition,our proton antagonist membrane outperforms the commercial anion exchange membrane in both conductivity and oxidation resistance lifetime,which are crucial for large scale electrolysis of carbon neutral chemicals.

关键词： CO_(2)reduction proton antagonist membrane electrode assembly

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High-performance amorphous In–Ga–Zn–O thin-film transistor nonvolatile memory with a novel p-SnO/n-SnO_(2) heterojunction charge trapping stack

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Chinese Physics B 2023年第1期32卷 580-584页

作者：熊文霍景永吴小晗刘文军张卫丁士进 State Key Laboratory of ASIC and System School of MicroelectronicsFudan UniversityShanghai 200433China National Integrated Circuit Innovation Center Shanghai 201203China

Amorphous In–Ga–Zn–O(a-IGZO)thin-film transistor(TFT)memories with novel p-SnO/n-SnO_(2) heterojunction charge trapping stacks(CTSs)are investigated comparatively under a maximum fabrication temperature of 280℃.Compared to a single p-SnO or n-SnO_(2) charge trapping layer(CTL),the heterojunction CTSs can achieve electrically programmable and erasable characteristics as well as good data *** the two CTSs,the tunneling layer/p-SnO/nSnO_(2)/blocking layer architecture demonstrates much higher program efficiency,more robust data retention,and comparably superior erase *** resulting memory window is as large as 6.66 V after programming at 13 V/1 ms and erasing at-8 V/1 ms,and the ten-year memory window is extrapolated to be 4.41 *** is attributed to shallow traps in p-SnO and deep traps in n-SnO_(2),and the formation of a built-in electric field in the heterojunction.

关键词： nonvolatile memory a-IGZO thin-film transistor(TFT) charge trapping stack p-SnO/n-SnO_(2)heterojunction

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Permutation-Based Approximate Multiplier with High Accuracy 15

Permutation-Based Approximate Multiplier with High Accuracy

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15th IEEE International Conference on asic, asicON 2023

作者： Li, Kunlong Dai, Yunfei Li, Zhen Wang, Lingli Fudan University State Key Laboratory of ASIC and System Shanghai China

ISBN: (纸本)9798350312980

In computationally complex applications, the tolerance of errors and the restriction of energy consumption stimulate the research into approximate computing, a promising methodology to trade off the hardware cost and accuracy loss. In this paper, we propose an automated design method to generate approximate substitutes for a widely-used arithmetic operation - multiplication. The partial products of two rows are compressed by logical operations, and the partial products in adjacent columns can also be permutated. Our proposed 8-bit multiplier can achieve 19.6% higher accuracy, 3.8% lower power, and 11.3% less area than the best reproduced approximate multiplier under the uniform distribution. Compared with an exact multiplier, the reduction in power and area is 36.2% and 32.8%, respectively. To evaluate the design, we carry out a simulation in image blurring with a 5∗5 Gaussian kernel by replacing all the multiplications. The Peak Signal-to-Noise Ratio (PSNR) between the exact multiplier and ours can attain 50.10 dB, which outperforms all other reproduced approximate multipliers. © 2023 IEEE.

关键词： Approximate computing image blurring permutation

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Exhaustive Application-Dependent Testing for FPGA Interconnect Resources 17

Exhaustive Application-Dependent Testing for FPGA Interconne...

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17th IEEE International Conference on Solid-state and Integrated Circuit Technology, ICSICT 2024

作者： Chen, Wenwei He, Xinyu Ding, Tongshu Wang, Jian Lai, Jinmei School of Microelectronics Fudan University State Key Laboratory of ASIC and System Shanghai201203 China

ISBN: (纸本)9798350361834

Up to now, in the field of application-dependent testing for FPGA interconnect resources, the most widely used method is single-term function method, and the most accurate fault model is asymmetric bridging fault model. In this paper, a new fault model called Boolean bridging fault model is proposed, which is a superset of asymmetric bridging fault model. Based on single-term function method, we minimize the number of test configurations to the greatest extent possible, and theorems in set theory ensure that the result is optimal for both asymmetric bridging fault model and Boolean bridging fault model. Moreover, for special cases called feedback bridging faults, the study demonstrates that repeated sampling is a simple method that can achieve high coverage. © 2024 IEEE.

关键词： Integrated circuit testing

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Efficient FPGA Routing Architecture Exploration Based on Two-Stage MUXes 15

Efficient FPGA Routing Architecture Exploration Based on Two...

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15th IEEE International Conference on asic, asicON 2023

作者： Zhang, Jide Zhu, Kaixiang Shi, Kaichuang Wang, Lingli Zhou, Hao Fudan University State Key Laboratory of ASIC and System Shanghai China

ISBN: (纸本)9798350312980

Employing large routing multiplexers (MUXes) in FPGA results in significant area and delay overheads. Hence, the two-stage cascaded structure with small MUXes can reduce the area and delay effectively. However, the manual design of a two-stage MUX topology is challenging to find optimal architecture. An automatic switch pattern exploration framework is proposed based on a novel routing architecture, TSRB (Two-Stage MUX Routing Block), which consists of two-stage MUXes in switch box (SB) and local interconnection block (LIB). The framework can enable the router to select commonly used switches based on the usage of switch connections under the premise of solving congestion, leading to a minimal set of switch types used in the architecture. The TSRB switch pattern is generated aided by a pre-exploration method to avoid manual design. The pattern optimization is then followed by two-stage MUX exploration. Our exploration framework can generate a TSRB switch pattern and optimize the pattern by pruning more than half of the switch connections, achieving an average 7% shorter critical path delay with a 5% area reduction compared to the one-stage large MUX routing architecture. © 2023 IEEE.

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A 1.8μA, 202 ns Fast Transient Response Output Capacitor-Less LDO with Dual Power Transistors 5

A 1.8μA, 202 ns Fast Transient Response Output Capacitor-Le...

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5th International Conference on Circuits and systems, ICCS 2023

作者： Yao, Chang Yi, Ting State Key Laboratory of Asic and System Fudan University Shanghai China

ISBN: (纸本)9798350308273

In this paper, an output capacitor-less low dropout (LDO) regulator with low power consumption and fast transient response is proposed. The dual power transistors are adaptively activated based on the load current. Furthermore, dynamic biasing techniques are utilized to enhance the response speed of the error amplifier. During transient response, the dynamic current is increased by adjusting the resistance of the bias stage after detecting the voltage fluctuation of the amplifier, and the quiescent current recovers to low levels in the steady state. The proposed LDO is implemented in the TSMC 180 nm process, and the simulation results show that the quiescent current of LDO is about 1.8 μA. When the load current varies between 100 μA and 10mA within 500 ns, the overshoot and undershoot voltages are 16mV and 140 mV, respectively, and the recovery time is 202 ns. © 2023 IEEE.

关键词： Transient analysis

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109.9-dB DR and 17.9-Bit ENOB Dynamic Zoom CDC Design for Audio Applications 5

109.9-dB DR and 17.9-Bit ENOB Dynamic Zoom CDC Design for Au...

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5th International Conference on Circuits and systems, ICCS 2023

作者： Zhang, Daiyu Yi, Ting Fudan University State Key Laboratory of Asic and System Shanghai China

ISBN: (纸本)9798350308273

Capacitive sensors are one of the most widely used sensors today. In recent years, High resolution has assumed a paramount role in sensor design, guaranteeing precise measurement outcomes. Quantification to the aF level is urgently needed. This paper presents the first dynamic Zoom capacitance to digital converter (CDC) incorporating noise coupling (NC) technology, which is intended for high-precision sensor applications in the audio domain. The proposed dynamic CDC is a hybrid of a high-resolution ΔΣ modulator (ΔΣM) and a high-efficiency SAR-based CDC to achieve better performance. It is implemented in the TSMC 180 nm process, and the simulation results show that it achieves 109.9dB DR and 109.3dB SNR within the bandwidth of 20kHz, consuming 81μW from a 1.2V supply. These advancements are accomplished through the combined utilization of coarse and fine conversions, noise coupling techniques, SAR-assisted multi-bit quantizers, and operational transconductance amplifiers (OTAs) based on dynamic bias inverters. © 2023 IEEE.

关键词： Capacitive sensors

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An Enhanced Packing Algorithm for FPGA Architectures without Local Crossbar 15

An Enhanced Packing Algorithm for FPGA Architectures without...

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15th IEEE International Conference on asic, asicON 2023

作者： Wang, Yuanqi Shi, Kaichuang Wang, Lingli Fudan University State Key Laboratory of ASIC and System Shanghai China

ISBN: (纸本)9798350312980

In the EDA process of FPGA, VTR (Verilog-to-Routing) is a commonly used open-source CAD tool in the academic community, and VPR (Versatile Place and Route) is the back-end process of VTR. The packing algorithm in VPR is a seed-based architecture-aware algorithm, which has strong versatility. However, the packing density is low for CLB architectures without local crossbar interconnect in the commercial FPGAs, which results in long critical path delays in circuits. To solve this problem, this paper optimizes the packing algorithm in VPR by adding a virtual crossbar in CLB, aiming to improve the internal utilization of each CLB and decrease the critical path delay of the circuit. The experimental result shows that it can reduce the average number of packed CLBs by 56.51% and the average critical path delay by 9.14% after the packing algorithm enhancement. © 2023 IEEE.

关键词： CLB Crossbar FPGA Packing Algorithm

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Exploration of FPGA PLB Architecture Base on LUT and Microgates

Exploration of FPGA PLB Architecture Base on LUT and Microga...

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2023 International Symposium of Electronics Design Automation, ISEDA 2023

作者： Shi, Xinyu Yang, Moucheng Li, Zhen Zhu, Kaixiang Wang, Lingli Fudan University State Key Laboratory of ASIC and System Shanghai China

ISBN: (纸本)9798350304510

Because of the logic redundancy of look-up table (LUT) based field programmable gate array (FPGA), we explore a series of programmable logic block (PLB) architectures to increase logic density by adding different kinds of microgates including AND gate and exclusive-OR gate. Because individual LUT inputs have different delays to the output, adding microgates to the shortest input-output path does not influence the LUT critical path delay. To evaluate the proposed PLB architectures, the Boolean matching based on disjoint-support decomposition (DSD) library in ABC is used to realize technology mapping and followed by VPR 8.0 to pack, place and route. Evaluation results based on VTR and Koios benchmarks show that the proposed PLB architecture by adding two AND gates to LUT6 can achieve the best performance, which reduces the logic depth, the utilization of PLBs, and the critical path delay by 19.8%, 4.36%, and 6.25% respectively on average compared to Intel Stratix-10 PLB architecture in VTR. © 2023 IEEE.

关键词： Field programmable gate arrays (FPGA)

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Rabbit: An Efficient Verification Platform Base on Virtual Peripherals 15

Rabbit: An Efficient Verification Platform Base on Virtual P...

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15th IEEE International Conference on asic, asicON 2023

作者： Zhang, Zhengyi Yang, Yuanda Wang, Lingli Fudan University State Key Laboratory of ASIC and System Shanghai China

ISBN: (纸本)9798350312980

With the increasing complexity of digital circuit designs, functional verification has assumed a crucial role within the overall design flow. The current hardware design verification flow commonly entails either manually writing a testbench or downloading the design to an FPGA for verification. However, the former often results in errors in hardware operation due to inadequate stimulus, while the latter necessitates substantial physical peripheral support, making it impractical to integrate all the required peripherals on a single board. To address these issues, this paper presents a novel open-source verification platform called Rabbit, which facilitates interactive verification by reading signals from the FPGA board to the PC and sending signals from the PC to the FPGA. The proposed approach is user-friendly, effective, and rapid, thereby ensuring thorough verification. Rabbit supports user-added components to provide high flexibility and a high operating frequency, 50 kHz, which is up to approximately 11.7 times faster than the current commercial tool based on the same hardware board. © 2023 IEEE.

关键词： FPGA hardware design verification virtual peripherals

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