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Design and Analysis of 8 Bit Fully Segmented Digital to Analog Converter

Design and Analysis of 8 Bit Fully Segmented Digital to Anal...

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International Conference on Recent Advances in Engineering & Computational Sciences

作者： Arpit Kumar Baranwal Anurag Balwinder Singh ACSD Centre for Development of Advanced Computing

ISBN: (纸本)9781467382540

This paper presents design of an 8-bit 1.8V fully segmented digital to analog converter (DAC) using 180nm CMOS technology. DAC is an essential part of digital signal processor. Digital to analog converter is employed in processing of digital signals and providing analog output in the form of current or voltage for corresponding binary input. The differential non linearity of a DAC shows variation in output corresponding to 1LSB change at input that is accuracy of data conversion. To achieve low non linearity or more accurate data conversion a DAC is designed with unary coding or a fully segmented digital to analog converter with current steering technique. The INL and DNL achieved in this research work are 0.145LSB and 0.013LSB respectively. The power consumption is simulated as 99.67mW.

关键词： Fully Segmented Current steering dac

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On board EMG signal compression for portable devices-a study

On board EMG signal compression for portable devices-a study

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2013 International Conference on Machine Intelligence Research and Advancement, ICMIRA 2013

作者： Sharma, Sushant Singh, Mandeep ACSD Centre for Development of Advanced Computing Mohali India Engineer Digital Electronics and Communication Division Centre for Development of Advanced Computing Mohali India

ISBN: (纸本)9780769550138

Electromyography signals are used for biomedical applications and clinical diagnosis. This paper presents a system to acquire high quality EMG (electromyography) signal and compress it for high data transfer rate. For acquiring EMG signals we are using off-the-shelf integrated circuit AFE which generates 24 bit data stream output. After acquiring the signal from front end amplifier, the signal is processed (filtration, compression). This is achieved by making use of MSP430 MCU (micro controller). We are using AFE and MSP430 because it is less power consuming, reliable, and both are compatible with each other. The detail of the hardware and software is explained in the further section of the paper. This paper also describes the compression algorithm. Compression is done so that whenever the data is send wirelessly using Bluetooth, Zigbee etc, it requires less bandwidth. © 2013 IEEE.

关键词： Data transfer

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Performance Analysis and Implementation of Scalable Encryption Algorithm on FPGA

Performance Analysis and Implementation of Scalable Encrypti...

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International Conference on Machine Intelligence and Research Advancement (ICMIRA)

作者： Ekta Jolly Dilip Kumar Balwinder Singh ACSD Centre for Development of Advanced Computing (C-DAC) Mohali India

Scalable Encryption Algorithm (SEA), a parametric block cipher finds its application for confined processing resources and throughput requirement. It is an efficient solution for small embedded application and initially used for software implementation in controllers, smart card, processors and many other resources constrained systems (e.g. sensor networks RFIDs). In this paper, an algorithm is presented whose performance is investigated in recent field programmable array devices. For this purpose different modules of algorithm like encrypt block, decrypt block and key Schedule are written separately and then integrated in an iterative loop architecture thus allowing efficient combination of encryption, decryption and "on-the-fly" key derivation. The synthesis results for area utilization, working frequency and throughput are verified on target platform Virtex-5.

关键词： Encryption Ciphers Algorithm design and analysis Schedules Software algorithms Program processors

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On Board EMG Signal Compression for Portable Devices - A Study

On Board EMG Signal Compression for Portable Devices - A Stu...

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International Conference on Machine Intelligence and Research Advancement (ICMIRA)

作者： Sushant Sharma Mandeep Singh ACSD Centre for Development of Advanced Computing Mohali India Division Centre for Development of Advanced Computing Engineer Digital Electronics and Communication Mohali India

关键词： Electromyography Electrodes Noise Muscles Conferences Compression algorithms Quantization (signal)

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Novel High Gain Low Noise CMOS Instrumentation Amplifier for Biomedical Applications

Novel High Gain Low Noise CMOS Instrumentation Amplifier for...

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International Conference on Machine Intelligence and Research Advancement (ICMIRA)

作者： Akshay Goel Gurmohan Singh Academic & Consultancy Services Division (ACSD) Centre for Development of Advanced Computing (C-DAC) Mohali India Digital Electronics & Communication Division (DECD) Centre for Development of Advanced Computing (C-DAC) Mohali India

This work describes a novel technique of designing a high gain low noise CMOS instrumentation amplifier for biomedical applications like ECG signal processing. A three opamp instrumentation amplifier have been designed by using two simple op-amps at the two input stages and a folded cascode opamp at the output stage. Both op-amps at the input and output are 2-stage. Most of the previous or earlier designed op-amp in literature uses same type of op-amp at the input and output stages of instrumentation amplifier. By using folded cascode op-amp at the output, we had achieved significant improvement in gain and CMRR. Transistors sizing plays a major role in achieving high gain and CMRR. To achieve a desirable common mode rejection ratio (CMRR), Gain and other performance metrics, selection of most appropriable op-amp circuit topologies & optimum transistor sizing was the main criteria for designing of instrumentation amplifier for biomedical applications. The complete instrumentation amplifier design is simulated using Cadence Spectre tool and layout is designed and simulated in Cadence Layout editor at 0.18μm CMOS technology. Each of the input two stage op-amp provides a gain and CMRR of 45dB and 72dB respectively. The output two stage folded cascode amplifier provides a CMRR of 92dB and a gain of 82dB. The design achieves an overall CMRR and gain of 92dB and 67db respectively. The overall power consumed by instrumentation amplifier is 263μW which is suitable for biomedical signal processing applications.

关键词： Instruments Noise Resistors Transistors Gain CMOS integrated circuits Layout

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64-Bits low power CMOS SRAM by using 9T cell and charge recycling scheme

64-Bits low power CMOS SRAM by using 9T cell and charge recy...

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2012 International Conference on Devices, Circuits and Systems, ICDCS 2012

作者： Singhal, Varun Kumar Singh, Balwinder Roorkee India ACSD Centre for Development of Advanced Computing Mohali India

ISBN: (纸本)9781457715457

Memory, the unit responsible for data and information storage, is the most populated module in present electronic devices. High-speed devices use Static Random Access Memory (SRAM) for data storage. The requirement in present scenario is low power devices. Keeping this point in view, this paper proposes Charge Recycling (CR) on 9T CMOS SRAM. The Proposed and conventional 64-bit SRAM has been designed and simulated for 250nm, 180nm and 130nm CMOS technologies. The 64-bit memory is organized in 8 x 8 form (i.e. 8 rows and 8 columns). Simulation results show the reduction in average write power is 78.22%, 77.15% and 66.66% at 250nm, 180nm and 130nm CMOS technologies respectively when compared with simulation results of conventional 6T SRAM for the same technologies. Simulation has been done at 100MHz and at 1.8 volts rail-to-rail voltage. © 2012 IEEE.

关键词： Recycling

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64-bits low power CMOS SRAM by using 9T cell and charge recycling scheme

64-bits low power CMOS SRAM by using 9T cell and charge recy...

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International Conference on Devices, Circuits and Systems (ICDCS)

作者： Varun Kumar Singhal Balwinder Singh College of Engineering Roorkee(COER) Roorkee India Centre for Development of Advanced Computing Mohali ACSD India

Memory, the unit responsible for data and information storage, is the most populated module in present electronic devices. High-speed devices use Static Random Access Memory (SRAM) for data storage. The requirement in present scenario is low power devices. Keeping this point in view, this paper proposes Charge Recycling (CR) on 9T CMOS SRAM. The Proposed and conventional 64-bit SRAM has been designed and simulated for 250nm, 180nm and 130nm CMOS technologies. The 64-bit memory is organized in 8 × 8 form (i.e. 8 rows and 8 columns). Simulation results show the reduction in average write power is 78.22%, 77.15% and 66.66% at 250nm, 180nm and 130nm CMOS technologies respectively when compared with simulation results of conventional 6T SRAM for the same technologies. Simulation has been done at 100MHz and at 1.8 volts rail-to-rail voltage.

关键词： Random access memory Transistors Logic gates Bismuth

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