Coarse-grained reconfigurable array( CGRA) has an advantage in the implementation of symmetric cryptog raphic algorithms with high performance and flexibility. S pecially, interconnection network is u
ISBN:
(纸本)9781467389808
Coarse-grained reconfigurable array( CGRA) has an advantage in the implementation of symmetric cryptog raphic algorithms with high performance and flexibility. S pecially, interconnection network is u
In this work, the dissolution and corrosion of cobalt (Co) films were investigated using solutions of aqueous mixtures of oxidant H2O2, and different inhibitors (1, 2, 4-triazole (TAZ), nicotinic acid (NA) and benzotr...
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A novel photodetector based on a silicon-on-insulator (SOI) substrate is demonstrated experimentally in this work. The device uses the interface coupling effect in an SOI transistor structure to amplify the photocurre...
A novel photodetector based on a silicon-on-insulator (SOI) substrate is demonstrated experimentally in this work. The device uses the interface coupling effect in an SOI transistor structure to amplify the photocurrent, and thus achieves extremely high responsivity up to 6×10 4 A/W. The responsivity of the device under ultraviolet (UV) light is much higher than that under visible and near-infrared light, which implies potential application in visible-blind UV detection. Furthermore, a MoS 2 gate is combined with the SOI-based photodetector to tune the response spectrum and shift it to the near-infrared band. With high reponsivity and tunable response spectrum, the ICPD device can find many interesting applications.
Electrical artifact cancellation is essential to the linearity improvement of neural signal detection systems. This paper aims to find the optimized method of electrical artifact cancellation for neural recording syst...
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Electrical artifact cancellation is essential to the linearity improvement of neural signal detection systems. This paper aims to find the optimized method of electrical artifact cancellation for neural recording systems. Three approaches are analyzed in terms of system complexity, artifact cancellation performance and stability through simulation. According to the simulation results, the least mean square (LMS) adaptive filter shows the best artifact cancellation ability and robustness. The LMS-based artifact filtering algorithm is verified using Hardware Description Language (HDL).
Deblocking filter (DBF) is an efficient tool to reduce the bit rate in the latest video coding standard, High Efficiency Video Coding (HEVC). This work presents an SRAM-free deblocking filter VLSI architecture with hi...
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Deblocking filter (DBF) is an efficient tool to reduce the bit rate in the latest video coding standard, High Efficiency Video Coding (HEVC). This work presents an SRAM-free deblocking filter VLSI architecture with high throughput and efficiency. To avoid the usage of SRAM inside the DBF module, the basic filter unit (BFU) is designated as 8 x 8 block size and the vertical boundaries in 8 x 8 block will be filtered firstly followed by the horizontal. Besides, the block in & out and block filtering will be performed by pipeline to improve DBF throughput. Based on the proposed architecture, it takes 4 cycles to finish one BFU processing, one cycles for one boundary between two 4x4 blocks. The experimental result shows that our design can support 8K@120fps real-time video coding with TSMC 65nm process, which occupies 23.5K gates at 400NHz.
In the process of intra prediction of the High Efficiency Video Coding(HEVC), the calculation requirement is hugely increased. In order to solve this problem, we propose two algorithms, including a novel fast CU parti...
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In the process of intra prediction of the High Efficiency Video Coding(HEVC), the calculation requirement is hugely increased. In order to solve this problem, we propose two algorithms, including a novel fast CU partition decision algorithm and a novel fast PU mode decision algorithm, for HEVC intra coding based on convolutional neural network(CNN). We can directly predict the CU partition structure without the reference to the information of its neighboring CU, and replace the RMD process with our CNN to get the PU candidate list. The experiments show that compared to the former CNN algorithms, our algorithms could save more than 20% coding time while ensuring the coding quality of pictures.
Block copolymer (BCP) lithography as a low-cost and simple process emerges to become an important patterning technique in microelectronic manufacturing. In this work, self-assembly of a triblock copolymer was used to ...
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Block copolymer (BCP) lithography as a low-cost and simple process emerges to become an important patterning technique in microelectronic manufacturing. In this work, self-assembly of a triblock copolymer was used to prepare silicon nanowire FinFET devices on the SOI substrate. The original pattern was formed on the block copolymer layer via self-assembly, and then transferred to the Si layer by dry etching that stops at the interface of Si and box oxide. The minimum critical dimension of the device can be as small as 8 nm, and the performance is extensively evaluated. This type of FinFET device shows high transconductance (g m ) 150 μS, signifies extremely low off current (I OFF ) ~50 pA, and high on/off current ratio (I ON /I OFF ) up to 3×10 6 .
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