Fast Fourier transformation (FFT) is a key operation in digital communication systems. Different communication standards require various FFT length and precision. In this paper, we present a low power Application-Spec...
详细信息
ISBN:
(纸本)9781467348638
Fast Fourier transformation (FFT) is a key operation in digital communication systems. Different communication standards require various FFT length and precision. In this paper, we present a low power Application-Specific Instruction-set Processor (ASIP) for variable length (16-point-4096-point) and bit precision (8-bit - 16-bit) to meet different requirements. We use scalable multipliers to construct the butterfly unit, which support both 8-bit and16-bit operation. The order of butterfly operation is adjusted to reduce twiddle-factorROM accesses, so as to reduce overall power consumption efficiently. Clock Gating is implemented to shut down processor's pipeline during the FFT processin terms of special low power demands. Special Instructions are tailored to make full use of the flexible hardware.
CoMo alloys as copper diffusion barriers were investigated in this *** thermal stability was studied after annealing,which was measured by FPP, XRD,SEM and *** to the electrical test,we carried out a new p-cap structu...
详细信息
CoMo alloys as copper diffusion barriers were investigated in this *** thermal stability was studied after annealing,which was measured by FPP, XRD,SEM and *** to the electrical test,we carried out a new p-cap structure to *** breakdown electrical field and C-V properties were measured at 150℃.Both the thermal test and electrical results show CoMo is a potential diffusion barrier.
In this paper, an efficient packing algorithm based on constraint satisfaction problem technique is proposed for contemporary FPGA CLB architecture. No matter how complex the architecture is, there are a limited numbe...
详细信息
In this paper, an efficient packing algorithm based on constraint satisfaction problem technique is proposed for contemporary FPGA CLB architecture. No matter how complex the architecture is, there are a limited number of patterns, which can implement all functionalities of FPGA CLB logic. All the patterns are pre-designed and known as reference circuits. The proposed algorithm then matches the reference circuits from the given user logic circuit using specific constraints. Due to complex architecture of FPGA, to enumerate all the reference circuits in a fine-grain manner is impractical. Consequently, coarse-grain manner is adapted in the paper to overcome this problem. The experimental results show that the proposed algorithm achieves comparable performance in area and speed compared with literatures.
We propose a novel scheme to realize large group delay in a single ring resonator with an OFDM transmitter. The fundamental trade-off between transmission bandwidth and delay can be addressed with this new buffer. ...
详细信息
This paper explores two low temperature technological developments related to future n-MOSFETs using III-V semiconductors as channel materials. (1). It was found that Yb-GaAs Schottky contact with RTA at 500°C fo...
详细信息
A logic-process embedded DRAM with 2T multi-Vth PMOS gain cell with one high-Vth for retention enhancement and one low-Vth transistors for fast read speed is *** improve the write speed,the write back step and sense s...
详细信息
ISBN:
(纸本)9781467324748
A logic-process embedded DRAM with 2T multi-Vth PMOS gain cell with one high-Vth for retention enhancement and one low-Vth transistors for fast read speed is *** improve the write speed,the write back step and sense step are separated,and the write before sense schemes are adopted to improve write speed and suppress the noise disturbance to adjacent bitlines. The simulation results illustrate that the write cycle of memory is 3ns which corresponding to 333MHz operating *** cell size is 64F2 and is 40%of SRAM in the same process generation.
Analytic models for channel potential and the subthreshold swing of the dual-material double-gate (DMDG) metal-oxide-semiconductor field-effect transistor (MOSFET) are presented. To avoid the complexity of the computa...
详细信息
Analytic models for channel potential and the subthreshold swing of the dual-material double-gate (DMDG) metal-oxide-semiconductor field-effect transistor (MOSFET) are presented. To avoid the complexity of the computation, Poisson's equation (PE) is solved through the entire channel region, and an analytic expression for electric potential is obtained. Based on the potential model, subthreshold swing is obtained. Model results match with Medici simulations very well. The results will provide some guidance for the application of the device in integrated circuits.
We theoretically and numerically analyze the multi-carriers generation scheme based on only integrated IQ modulator. Flat and stable 11 carriers are obtained and 112Gb/s PM-QPSK experiment over a single subcarrier has...
详细信息
ISBN:
(纸本)9781557529381
We theoretically and numerically analyze the multi-carriers generation scheme based on only integrated IQ modulator. Flat and stable 11 carriers are obtained and 112Gb/s PM-QPSK experiment over a single subcarrier has been demonstrated.
The preparation of porous ceramic scaffolds with nano-hydroxyapatite (HA) whiskers was reported in this work. By adding kalium ion and adjusting the pH value of solution, the thermal stability of nano-HA whiskers were...
详细信息
暂无评论