Radio frequency identification (RFID) is a technology for automatic object identification. It has wide applications in many areas such as manufacturing, transportation, healthcare, and so on. However, many RFID system...
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Radio frequency identification (RFID) is a technology for automatic object identification. It has wide applications in many areas such as manufacturing, transportation, healthcare, and so on. However, many RFID systems are suffering from security issues. In this paper, we present an implementation of a secure UHF RFID tag baseband with a Hummingbird (HB) cryptographic engine using the SMIC 0.13μm technology. An improvement of the Gen2 protocol based on our secure engine is proposed to enhance security. The implementation results show that the area of our baseband is 16,986 gate equivalents and the secure engine takes 23.6% of the entire die area. The overall power consumption of our baseband is 30.67μW at a clock frequency of 1.28MHz and with 1.2V power supply, which is suitable for resource-constrained RFID tags.
This paper presents a statistical method to build up interconnect timing library of static timing analysis for FPGA design. To overcome a large number of negative values in the traditional interconnect timing libr...
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This paper presents a statistical method to build up interconnect timing library of static timing analysis for FPGA design. To overcome a large number of negative values in the traditional interconnect timing library, the statistical method is introduced. The experimental results show that the proposed method could improve the positive ratio and achieve up to 22.35％ on average. Compared to the tested delay results on the FPGA chip, the delay error rate can be reduced from 13.58％ to 11％.
Face detection has been playing an important role in more and more fields, which makes it necessary and urgent to have its architecture reconfigurable to satisfy different requirements on detection capabilities. T...
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Face detection has been playing an important role in more and more fields, which makes it necessary and urgent to have its architecture reconfigurable to satisfy different requirements on detection capabilities. The paper proposes a face detection architecture, which could be adjusted by the users according To the environment, the sensor resolution, the different requirements of detection accuracy and speed. This user adjustable mode makes the reconfiguration simple and efficient, and especially benefits for the application of portable mobile terminals whose working condition often changes frequently. Experimental results show that the reconfiguration of the architecture is very reasonable in face detection and synthesized report also indicates its advantage on speed and accuracy.
Highly integrated contemporary SRAM-based Field Programmable Gate Arrays (FPGAs) lead to high occurrence-rate of transient faults induced by Single Event Upsets (SEUs) in FPGAs' configuration memory. In this p...
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Highly integrated contemporary SRAM-based Field Programmable Gate Arrays (FPGAs) lead to high occurrence-rate of transient faults induced by Single Event Upsets (SEUs) in FPGAs' configuration memory. In this paper, Fudan Design Environment (FDE) Triple Module Redundancy (TMR) approach for design triplication has been devised to meet highreliability design on FDP2008. Throughput Logic, feedback logic, I/O logic and special feature such as Shift Register LUTs (SRLs) and constant logic are treated differently to effectively mitigate the effects of the SEU faults.
To enhance security in WLAN, CCMP is introduced in IEEE 802.1 1i. This paper presents a heterogeneous multi-core architecture based on NoC to support highspeed CCMP application. Four general processors and twelve ...
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To enhance security in WLAN, CCMP is introduced in IEEE 802.1 1i. This paper presents a heterogeneous multi-core architecture based on NoC to support highspeed CCMP application. Four general processors and twelve security ASIPs are *** a 4×4 mesh NoC. A modified PTLU is implemented in each ASIP to accelerate AES operations. Task parallelism in CCMP is exploited to obtain high throughput. Synthesized in SMIC 0.13 μm CMOS technology, the proposed system measures a hardware cost of 3.08M gates. Experiment results show that the system achieves a throughput of 787Mbps at 84MHz.
This paper presents a high performance design for Context-Based Adaptive- Variable Length-Coding (CAVLC) used in the H.264/AVC standard. To reduce the cycles of processing one macroblock (MB), a two-stage residual...
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This paper presents a high performance design for Context-Based Adaptive- Variable Length-Coding (CAVLC) used in the H.264/AVC standard. To reduce the cycles of processing one macroblock (MB), a two-stage residual encoder is proposed to make the scan and encode stage work simultaneously. The scan engine scans two coefficients at each cycle. Parallel encoder for two levels and parallel encoder for two runs are adopted to accelerate the encoder engine. Only 228 cycles at most are needed to process one MB. Due to the existence coded block pattern (CBP) decided skip block mode, our experiment shows only 160 cycles are needed on the average. The proposed CAVLC encoder can support 4Kx2K @30fps (frames per second) real-time encoding at 250 MHz and the gate count is only about 16k.
In this paper, genetic algorithm (GA) using parallel tabular technique is presented for the optimization of mixed polarity Reed Muller and mixed polarity dual Reed Muller functions. The algorithm is to find optimal so...
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This paper presents a security processor based on MIPS 4KE architecture which extends security functions of AES and ECC. Due to the different features of AES and ECC encryptions, two dedicated hardware units are e...
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This paper presents a security processor based on MIPS 4KE architecture which extends security functions of AES and ECC. Due to the different features of AES and ECC encryptions, two dedicated hardware units are employed. One is the AES function unit which is integrated into the pipeline of this MlPS-like processor, and the other is the ECC unit which works as a coprocessor to implement asymmetric cryptographic algorithms. Moreover, the instruction set extensions(ISE) of MIPS for these security functions are developed. Therefore, our security processor is not only able to handle high-intensity encryption tasks, but also compatible to the leading software development tools of industry. At last, its functionality and high performance are verified by our experimental chip.
In this paper, a hardware/software co-design approach is proposed to parse the video bitstream which conforms to various video compression standards. The layered structure of the syntax elements in video bitstream...
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In this paper, a hardware/software co-design approach is proposed to parse the video bitstream which conforms to various video compression standards. The layered structure of the syntax elements in video bitstreams is analyzed. Then a hardware/software partition is proposed accordingly. Due to the high data rate, syntax elements in slice data and lower layers are commonly parsed by hardware. As for syntax elements in slice header and upper layers, we proposed a hw/sw co-design approach in order to combine the advantage of hardware acceleration and software flexibility, specific hardware accelerators are designed to parse these codes. But the parsing process of these codes in slice header and upper layer is controlled by software instead of hardware Finite state machine (FSM). This approach can speed up the process of Variable-Length Decoding (VLD) while it still has the flexibility to support multiple video coding standards.
There is a growing tendency for FPGA (Field Programmable Gate Array) IP (Intellectual Property) cores to be embedded in an SOC (system On a Chip). The embedded FPGA cores' can improve the flexibility of the SO...
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There is a growing tendency for FPGA (Field Programmable Gate Array) IP (Intellectual Property) cores to be embedded in an SOC (system On a Chip). The embedded FPGA cores' can improve the flexibility of the SOC chip. However, different SOC varies in the demands on the scale of FPGA tile array.. Therefore, a scalable FPGA generator is required. In this paper, an automatic layout generator to support user-defined FPGA array size is introduced and compared with the previous related works. This paper shows that the proposed layout generator based on FPGA tiles is more practical than the previous tools.
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