This paper presents an implementation of channel estimation for LTE downlink MIMO system on a multicore processor platform. With the development of wireless communication, it is gradually difficult for asic baseban...
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This paper presents an implementation of channel estimation for LTE downlink MIMO system on a multicore processor platform. With the development of wireless communication, it is gradually difficult for asic baseband processing solutions to adapt the rapidly changing communication requirements. Multicore solution for communication applications arises due to its programmability and reconfigurability. The multi-core processor platform is a mesh array of SIMD cores which is well suited for communication applications. A channel estimator with the throughput of 113.5Msymbol/s is realized by fully utilizing task-level parallelism, data-level parallelism and pipeline structure on multi-core processor platform
In this work, we investigate analytically quantum mechanical (QM) effects on the threshold voltage (VTH ) shift of the surrounding-gate (SG) MOSFETs. We show how VTH is influenced with QM effects with ...
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In this work, we investigate analytically quantum mechanical (QM) effects on the threshold voltage (VTH ) shift of the surrounding-gate (SG) MOSFETs. We show how VTH is influenced with QM effects with the considerations of (110)-silicon (Si) orientation and (100)-Si orientation. When the radius of an SG MOSFET is small (<3nm), the VTH shift will be significant, and one should be careful in the use of a device with an extremely small silicon body radius. The analytical results are compared with those obtained by B. Yu et al., and good agreement is observed.
A new LUT and carry structure embedded in the configurable logic block of FPGA is proposed. The LUT is designed to support both 4-input and 5-input structures, which can be configured by users' according to th...
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A new LUT and carry structure embedded in the configurable logic block of FPGA is proposed. The LUT is designed to support both 4-input and 5-input structures, which can be configured by users' according to their needs without increasing the complexity of interconnect structures. We also develop a new carry chain structure with fast and slow carry paths. The circuit is fabricated in 0.13um 1P8M 1.2/2.5/3.3V Logic CMOS technology. The measured results show a correct function of 4/5-input LUT and a speedup in carry performance of nearly 3 times over current architecture.
In this letter, we describe the impact of quadrature imbalance (QI) in the presence of frequency offset and phase drift in an optical coherent offset-quadrature phase-shift-keying (OQPSK) *** the time domain, QI tilts...
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In this letter, we describe the impact of quadrature imbalance (QI) in the presence of frequency offset and phase drift in an optical coherent offset-quadrature phase-shift-keying (OQPSK) *** the time domain, QI tilts and squeezes the square constellation into a diamond ***' more, frequency offset continuously rotates the *** the presence of both QI and frequency offset, the constellation becomes *** conjugate misalignment was realized in a 2×4 90° optical hybrid, and the Gram-Schmidt orthogonalization procedure (GSOP) was applied in our simulation to compensate for quadrature imbalance in the ***, the GSOP enabled a set of nonorthogonal samples to be transformed into a set of orthogonal ***, a time domain method was adopted to compensate for chromatic dispersion (CD) due to fiber ***, the frequency offset between the received optical signal and LO signal, which was 200MHz in our simulation, was estimated and corrected by the phase increment estimation ***, we recovered the ideal square constellation after carrier phase estimation.
A built-in self-test (BIST) scheme is presented for at-speed test of the novel Gain Cell-based embedded DRAM which can operate at the high frequency of 200MHz. This BIST implementation consists of instruction set ...
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A built-in self-test (BIST) scheme is presented for at-speed test of the novel Gain Cell-based embedded DRAM which can operate at the high frequency of 200MHz. This BIST implementation consists of instruction set architecture (ISA) and hardware. A 4stage pipeline for instruction execution makes atspeed test possible. Various kinds of tests, including single-address test, traversal test and refresh test, can be performed by executing different instruction combinations. An 8KB Gain Cell memory with the BIST is fabricated in 0.13μm CMOS technology. Silicon measurement on ATE shows that the BIST can perform at-speed test and measurement types mentioned above.
High-frequency ultrasonic transducer arrays are essential for efficient imaging in clinical analysis and nondestructive evaluation (NDE). However, the fabrication of piezoelectric transducers is really a great challen...
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Spectrum sensing is a key technology of cognitive radio. The goal of spectrum sensing in this context is to achieve a high detection probability in order to avoid causing interference to the primary licensed users...
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Spectrum sensing is a key technology of cognitive radio. The goal of spectrum sensing in this context is to achieve a high detection probability in order to avoid causing interference to the primary licensed users: Among the methods available for spectrum sensing, energy detection has been widely applied in hardware implementations. However, since previous work has been based on the traditional FFT, the side leakage problem makes it difficult to detect a primary user adjacent to a strong signal. In this paper, we propose an all-phase FFT based wideband spectrum sensing processor. Simulation results show that it can increase the probability of detection of a primary user that is adjacent in frequency to a strong signal. It can also improve the receiver operating characteristic curve. Hardware implementation requirements are also given.
This paper presents a Whole Annealing Genetic Algorithm (WAGA) to obtain a good circuit implementation among mixed polarity Reed-Muller expressions. By combining global searching ability of genetic algorithm and l...
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This paper presents a Whole Annealing Genetic Algorithm (WAGA) to obtain a good circuit implementation among mixed polarity Reed-Muller expressions. By combining global searching ability of genetic algorithm and local searching ability of simulated annealing, WAGA could achieve fast convergence. Apart from genetic operators such as crossover operator and mutation operator are used in genetic algorithm stage, it uses annealing operator at annealing stage. At the annealing stage, WAGA forms an intermediate population by selecting 2/3 population from previous generation and 2/3 population from current generation. Annealing operator is then applied to the intermediate population. To achieve an efficient CPU utilization, the calculation of the cost function of WAGA is based on a parallel manner, in which newly generated terms are obtained at one time. The results of tested benchmark show that the algorithm is highly effective for searching the best polarity and achieves 13% improvement on average in terms of CPU time.
This paper presents the design of a sub-exponent time-to-digital converter (TDC) that amplifies a time residue to improve both the time resolution and measurement range. The sub-exponent TDC quantizes the fraction...
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This paper presents the design of a sub-exponent time-to-digital converter (TDC) that amplifies a time residue to improve both the time resolution and measurement range. The sub-exponent TDC quantizes the fractional time difference with a cascading chain of 2× time amplifiers. A digitally self-calibrated TA circuit is developed to achieve large input range and stable gain. Simulation results show that implemented in SMIC 0.13μm CMOS, the proposed TDC can achieve a minimum resolution of 0.8ps, a measurement range of 14bits, and a power dissipation of 2mW at 60MHz.
In this paper, several frame synchronization schemes is examined under the scenario of Broadband Powerline Communication (BPL) with their merits and demerits illustrated. A method, mainly based on algorithm propose...
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In this paper, several frame synchronization schemes is examined under the scenario of Broadband Powerline Communication (BPL) with their merits and demerits illustrated. A method, mainly based on algorithm proposed by Minn with modification, is proposed and simulated under channels proposed by Open PLC European Research Alliance (OPERA). Threshold is set according to simulations for frame synchronization as well as Physical Protocol Data Unit (PPDU) identification. The proposed estimator has a RMS (Root Mean Square) of start point estimation three orders lower at least in comparison with legacy Schmidl and Cox estimator. Optimization schemes are also proposed to increase the hardware efficiency for the estimator. As much as 75% multiplications could be saved with only a slight degradation in estimation accuracy for the proposed estimator.
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