Single-carrier frequency domain equalization (SC-FDE), as a mature technique in wireless commutation, is widely researched for signal equalization and compensation utilizing high speed electronic devices such as DSP. ...
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In this paper, a novel and simple all-optical scheme for generating UWB monocycle pulses based on the nonlinear polarization rotation in an SOA is proposed and experimentally demonstrated. UWB spectrum generated from ...
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Recently, as the continual development of services and needs, people have a higher expectation on the optical communication system especially the passive optical network (PON). Deciding which kind of fiber to be the o...
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We demonstrate electrically-pumped roomtemperature continuous-wave lasing in InP-based micro-disc lasers with threshold current of 6.5mA. A non-concentric hole inside the disc is used to extract the light and control ...
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We demonstrate electrically-pumped roomtemperature continuous-wave lasing in InP-based micro-disc lasers with threshold current of 6.5mA. A non-concentric hole inside the disc is used to extract the light and control the lasing mode.
With increasing process variation, binning has become an important technique to improve the values of fabricated chips, especially in high performance microprocessors where transparent latches are widely used. In this...
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ISBN:
(纸本)9781605588001
With increasing process variation, binning has become an important technique to improve the values of fabricated chips, especially in high performance microprocessors where transparent latches are widely used. In this paper, we formulate and solve the binning optimization problem that decides the bin boundaries and their testing order to maximize the benefit (considering the test cost) for a transparentlylatched circuit. The problem is decomposed into three sub-problems which are solved sequentially. First, to compute the clock period distribution of the transparently-latched circuit, a sample-based SSTA approach is developed which is based on the generalized stochastic collocation method (gSCM) with Sparse Grid technique. The minimal clock period on each sample point is found by solving a minimal cycle ratio problem in the constraint graph. Second, a greedy algorithm is proposed to maximize the sales profit by iteratively assigning each boundary to its optimal position. Then, an optimal algorithm of O(n log n) runtime is used to generate the optimal testing order of bin boundaries to minimize the test cost, based on alphabetic tree. Experiments on all the ISCAS'89 sequential benchmarks with 65-nm technology show 6.69% profit improvement and 14.00% cost reduction in average. The results also demonstrate that the proposed SSTA method achieves an error of 0.70% and speedup of 110X in average compared with the Monte Carlo simulation. Copyright 2009 ACM.
To reduce chip-scale topography variation in Chemical Mechanical Polishing (CMP) process, dummy fill is widely used to improve the layout density uniformity. Previous researches formulated the dummy fill problem as a ...
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ISBN:
(纸本)9781605584973
To reduce chip-scale topography variation in Chemical Mechanical Polishing (CMP) process, dummy fill is widely used to improve the layout density uniformity. Previous researches formulated the dummy fill problem as a standard Linear Program (LP). However, solving the huge linear program formed by real-life designs is very expensive and has become the hurdle in deploying the technology. Even though there exist efficient heuristics, their performance cannot be guaranteed. In this paper, we develop a dummy fill algorithm that is both efficient and with provably good performance. It is based on a fully polynomial time approximation scheme by Fleischer [4] for covering LP problems. Furthermore, based on the approximation algorithm, we also propose a new greedy iterative algorithm to achieve high quality solutions more efficiently than previous Monte-Carlo based heuristic methods. Experimental results demonstrate the effectiveness and efficiency of our algorithms. Copyright 2009 ACM.
This paper reports a novel 3D RRAM concept using stackable multi-layer 1TXR memory cell structure for future high density application. Using an 8-layer metal of stacked 1TXR (X=64) as an example, the density is over ...
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ISBN:
(纸本)9781424448876
This paper reports a novel 3D RRAM concept using stackable multi-layer 1TXR memory cell structure for future high density application. Using an 8-layer metal of stacked 1TXR (X=64) as an example, the density is over 260% higher than that of the conventional single layer 1T1R structure. Corresponding operation algorithm is put forward for the first time, which can inhibit mis-write and mis-read caused by sneaking current and reduce power consumption.
Software Defined Radio (SDR) allows dynamically changing protocols and functions in order to provide flexible, multiple-standard services to users. A reconfigurable baseband architecture having a set of coarse-grained...
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In this paper, we present a new placement algorithm targeted on a modern FPGA with heterogeneous logic and routing resources. This algorithm divides the heterogeneous resources of an FPGA into different logic layers, ...
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In this paper, we present a new placement algorithm targeted on a modern FPGA with heterogeneous logic and routing resources. This algorithm divides the heterogeneous resources of an FPGA into different logic layers, obtains a good initial placement by a quadratic method, and then employs low-temperature simulated annealing on each logic layer to determine the final location for all modules. Experiment result shows that the algorithm not only gains a saving of runtime by 27% compared with the classical approach of Versatile Place and Route (VPR) while having the same performance, but is also highly adaptable to modern FPGAs which have heterogeneous logic and routing resources.
In this paper, we consider the general problem of mapping a given logic circuit onto an SRAM-based FPGA with programmable logic blocks of arbitrary architectures. We formulate the problem as a graph matching problem a...
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ISBN:
(纸本)9781424438471
In this paper, we consider the general problem of mapping a given logic circuit onto an SRAM-based FPGA with programmable logic blocks of arbitrary architectures. We formulate the problem as a graph matching problem and present an architecture-independent algorithm for this purpose. This algorithm also obtains a best area saving of 4% compared to architecture-dependent methods.
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